公开(公告)号：US07462527B2

公开(公告)日：2008-12-09

申请号：US11160705

申请日：2005-07-06

Applicant: Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

Inventor： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

Abstract translation: 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

公开(公告)号：US20080146039A1

公开(公告)日：2008-06-19

申请号：US11611212

申请日：2006-12-15

Applicant: Daewon Yang ,  Jeffery B. Maxson ,  Ann N. McDonald

Inventor： Daewon Yang ,  Jeffery B. Maxson ,  Ann N. McDonald

IPC: H01L21/283

CPC classification number: C23C16/50

Abstract: A method of processing wafers within a high density plasma chemical vapor deposition chamber comprises setting a plasma charge level within the chamber at a zero power level and, while the plasma charge level within the chamber is at the zero power level, moving a wafer into the chamber. Then, the method sets the plasma charge level to a second power level higher than zero after the wafer is moved into the chamber and performs a chemical vapor deposition process on the wafer within the chamber. After performing the chemical vapor deposition process, the method moves the wafer to a non-plasma region within the chamber. Then, after moving the wafer to the non-plasma region within the chamber, the method again sets the plasma charge level within the chamber at the zero power level. Next, after setting the plasma charge level within the chamber at the zero power level, the method opens the door of the chamber and, while the plasma charge level within the chamber is at the zero power level, the method removes the wafer from the chamber through the door of the chamber.

Abstract translation: 在高密度等离子体化学气相沉积室内处理晶片的方法包括在零功率水平下设置室内的等离子体电荷水平，并且在室内的等离子体电荷水平处于零功率水平的同时，将晶片移动到 房间。 然后，该方法将晶片移入腔室之后，将等离子体电荷电平设置为高于零的第二功率电平，并在腔室内的晶片上执行化学气相沉积工艺。 在执行化学气相沉积工艺之后，该方法将晶片移动到室内的非等离子体区域。 然后，在将晶片移动到室内的非等离子体区域之后，该方法再次将室内的等离子体电荷水平设置在零功率水平。 接下来，在将腔室内的等离子体充电水平设置在零功率水平之后，该方法打开腔室的门，并且在室内的等离子体充电水平处于零功率水平的同时，该方法将晶片从腔室 通过房间的门。

公开(公告)号：US07179760B2

公开(公告)日：2007-02-20

申请号：US10908833

申请日：2005-05-27

Applicant: Richard A. Conti ,  Thomas F. Houghton ,  Michael F. Lofaro ,  Jeffery B. Maxson ,  Ann H. McDonald ,  Yun-Yu Wang ,  Keith Kwong Hon Wong ,  Daewon Yang

Inventor： Richard A. Conti ,  Thomas F. Houghton ,  Michael F. Lofaro ,  Jeffery B. Maxson ,  Ann H. McDonald ,  Yun-Yu Wang ,  Keith Kwong Hon Wong ,  Daewon Yang

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L23/53238 ,  H01L21/28556 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

Abstract translation: 本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。 这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。 在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层 ）选择性。

公开(公告)号：US06914015B2

公开(公告)日：2005-07-05

申请号：US10605857

申请日：2003-10-31

Applicant: Michael P. Belyansky ,  Patricia Argandona ,  Gregory DiBello ,  Andreas Knorr ,  Daewon Yang

Inventor： Michael P. Belyansky ,  Patricia Argandona ,  Gregory DiBello ,  Andreas Knorr ,  Daewon Yang

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/762 ,  H01L21/8242 ,  H01L21/31

CPC classification number: H01L21/02164 ,  H01L21/02274 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76224 ,  H01L27/10844

Abstract: An HDP process for high aspect ratio gap filling comprises contacting a semiconductor substrate with an oxide precursor under high density plasma conditions at a first pressure less than about 10 millitorr, wherein said gaps are partially filled with oxide; and further contacting the substrate with an oxide precursor under high density plasma conditions at a second pressure greater than about 10 millitorr, wherein said gaps are further filled with oxide.

Abstract translation: 用于高纵横比间隙填充的HDP工艺包括在高密度等离子体条件下以低于约10毫托的第一压力使半导体衬底与氧化物前体接触，其中所述间隙部分地填充有氧化物; 并且在高密度等离子体条件下，在大于约10毫托的第二压力下进一步使基底与氧化物前体接触，其中所述间隙进一步用氧化物填充。

公开(公告)号：US08679938B2

公开(公告)日：2014-03-25

申请号：US13366576

申请日：2012-02-06

Applicant: Sunfei Fang ,  Oleg Gluschenkov ,  Byeong Y. Kim ,  Rishikesh Krishnan ,  Daewon Yang

Inventor： Sunfei Fang ,  Oleg Gluschenkov ,  Byeong Y. Kim ,  Rishikesh Krishnan ,  Daewon Yang

IPC: H01L21/20

CPC classification number: H01L27/10861 ,  H01L21/76224 ,  H01L29/66181 ,  H01L29/945

Abstract: A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.

Abstract translation: 在包括沟槽电容元件的器件的有源区中形成浅沟槽隔离（STI）的方法，包括金属板和高k电介质的沟槽电容元件包括在器件的有源区中蚀刻STI沟槽 ，其中所述STI沟槽直接邻近所述沟槽电容元件的金属板或高k电介质中的至少一个; 以及在所述STI沟槽中形成氧化物衬垫，其中所述氧化物衬垫选择性地形成到所述金属板或高k电介质，其中形成所述氧化物衬垫在约600℃或更低的温度下进行。

公开(公告)号：US08557649B2

公开(公告)日：2013-10-15

申请号：US13278301

申请日：2011-10-21

Applicant: Rajasekhar Venigalla ,  Michael Vincent Aquilino ,  Massud A. Aminpur ,  Michael P. Belyansky ,  Unoh Kwon ,  Christopher Duncan Sheraw ,  Daewon Yang

Inventor： Rajasekhar Venigalla ,  Michael Vincent Aquilino ,  Massud A. Aminpur ,  Michael P. Belyansky ,  Unoh Kwon ,  Christopher Duncan Sheraw ,  Daewon Yang

IPC: H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/76283

Abstract: Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.

Abstract translation: 公开了用于控制半导体结构的高度的方法。 无定形碳被用作控制高度变异性的停止层。 在一个实施例中，控制用于晶体管的替换金属栅极的高度。 在另一个实施例中，控制浅沟槽隔离区的台阶高度。

公开(公告)号：US20130102125A1

公开(公告)日：2013-04-25

申请号：US13278301

申请日：2011-10-21

Applicant: Rajasekhar Venigalla ,  Michael Vincent Aquilino ,  Massud A. Aminpur ,  Michael P. Belyansky ,  Unoh Kwon ,  Christopher Duncan Sheraw ,  Daewon Yang

Inventor： Rajasekhar Venigalla ,  Michael Vincent Aquilino ,  Massud A. Aminpur ,  Michael P. Belyansky ,  Unoh Kwon ,  Christopher Duncan Sheraw ,  Daewon Yang

IPC: H01L21/762 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/76283

Abstract: Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.

Abstract translation: 公开了用于控制半导体结构的高度的方法。 无定形碳被用作控制高度变异性的停止层。 在一个实施例中，控制用于晶体管的替换金属栅极的高度。 在另一个实施例中，控制浅沟槽隔离区的台阶高度。

公开(公告)号：US20120190203A1

公开(公告)日：2012-07-26

申请号：US13434934

申请日：2012-03-30

Applicant: Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

Inventor： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

IPC: H01L21/311

CPC classification number: C23C16/507 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45578 ,  C23C16/4586 ,  C23C16/56 ,  H01J37/20 ,  H01J37/321 ,  H01J2237/20207 ,  H01J2237/3323 ,  H01L21/31608 ,  H01L21/3185 ,  H01L27/10867

Abstract: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

Abstract translation: 通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。 第二极性可以与第一极性相反。 额外的植入物可以减少第二细胞中的ESR。

公开(公告)号：US07851376B2

公开(公告)日：2010-12-14

申请号：US12364088

申请日：2009-02-02

Applicant: Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

Inventor： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02274 ,  C23C16/345 ,  C23C16/505 ,  H01L21/0217 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

Abstract translation: 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

公开(公告)号：US20090294923A1

公开(公告)日：2009-12-03

申请号：US12128772

申请日：2008-05-29

Applicant: Huilong Zhu ,  Yanfeng Wang ,  Daewon Yang ,  Haujie Chen

Inventor： Huilong Zhu ,  Yanfeng Wang ,  Daewon Yang ,  Haujie Chen

IPC: H01L23/00

CPC classification number: H01L23/3192 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A structure comprises at least one transistor on a substrate, an insulator layer over the transistor, and an ion stopping layer over the insulator layer. The ion stopping layer comprises a portion of the insulator layer that is damaged and has either argon ion damage or nitrogen ion damage.

Abstract translation: 一种结构包括在衬底上的至少一个晶体管，晶体管上的绝缘体层，以及绝缘体层上的离子阻挡层。 离子停止层包括被破坏并具有氩离子损伤或氮离子损伤的绝缘体层的一部分。