公开(公告)号：US06934900B1

公开(公告)日：2005-08-23

申请号：US09887783

申请日：2001-06-25

Applicant: Chuang Cheng ,  Chih-Tsun Huang ,  Jing-Reng Huang ,  Cheng-Wen Wu

Inventor： Chuang Cheng ,  Chih-Tsun Huang ,  Jing-Reng Huang ,  Cheng-Wen Wu

IPC: G01R31/28 ,  G01R31/3181 ,  G06F17/50 ,  G11C29/00 ,  G11C29/56

CPC classification number: G11C29/56004 ,  G01R31/31813 ,  G11C29/56

Abstract: A test pattern generation and comparison circuit creates test pattern stimulus signals for and evaluates response signals from logic or memory such as random access memory (RAM). It utilizes both parallel and serial interfaces to the logic/memory under test. The test pattern generation and comparison circuit further provides a method for testing logic and memory utilizing built-in self test (BIST) techniques. The method uses a programmable logic/memory commands which are translated into physical logic signals and timings for the logic or memory under test. The results of the test pattern generated and applied to the logic or memory are compared to expected results. The result of the comparison is a pass/fail designation. In addition, the comparison of the expected test results with the actual test results provides information on the exact location of the failure. Also, since the test pattern generation and comparison circuit architecture is compatible with hardware description languages such as Verilog HDL or VHDL, the test pattern generation and comparison circuit can be automatically generated with a silicon compiler.

Abstract translation: 测试模式生成和比较电路为诸如随机存取存储器（RAM）等逻辑或存储器的响应信号创建测试模式激励信号并对其进行评估。 它将并行和串行接口连接到被测逻辑/内存。 测试图形生成和比较电路还提供了一种利用内置自检（BIST）技术来测试逻辑和存储器的方法。 该方法使用可编程逻辑/存储器命令，这些命令被转换为被测逻辑或存储器的物理逻辑信号和定时。 将生成并应用于逻辑或存储器的测试模式的结果与预期结果进行比较。 比较结果是通过/失败指定。 此外，预期测试结果与实际测试结果的比较提供了有关故障确切位置的信息。 此外，由于测试模式生成和比较电路架构与诸如Verilog HDL或VHDL的硬件描述语言兼容，所以测试模式生成和比较电路可以用硅编译器自动生成。

公开(公告)号：US08762813B2

公开(公告)日：2014-06-24

申请号：US12781744

申请日：2010-05-17

Applicant: Yu-Shuen Tang ,  Chuang Cheng

Inventor： Yu-Shuen Tang ,  Chuang Cheng

IPC: G11C29/00

CPC classification number: H03M13/1105 ,  G06F11/10 ,  G06F11/1016 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/353 ,  H03M13/3707 ,  H03M13/6511 ,  H03M13/6513 ,  H03M13/6516

Abstract: A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different error corrections with different parameters. The system also includes means for providing a selected parameter to the ECC codec for initializing the ECC codec. The parameter used for initializing the ECC codec is an error-free parameter.

Abstract translation: 公开了一种用于存储器件或设备的多个纠错码（ECC）的可配置编码系统和方法。 该系统包括ECC编解码器，其选择性地执行具有不同参数的不同错误校正。 该系统还包括用于将ECC选择参数提供给ECC编解码器以便初始化ECC编解码器的装置。 用于初始化ECC编解码器的参数是无错参数。

公开(公告)号：US08332607B2

公开(公告)日：2012-12-11

申请号：US12183229

申请日：2008-07-31

Applicant: Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

Inventor： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract translation: 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。

公开(公告)号：US20120233401A1

公开(公告)日：2012-09-13

申请号：US13043334

申请日：2011-03-08

Applicant: Hsingho LIU ,  Fuja SHONE ,  Chuang CHENG ,  Yu-Shuen TANG

Inventor： Hsingho LIU ,  Fuja SHONE ,  Chuang CHENG ,  Yu-Shuen TANG

IPC: G06F12/00

CPC classification number: G06F13/1605

Abstract: An embedded memory system is disclosed. A main interface is configured to communicate with an electronic system via a main bus. A memory-sharing auxiliary interface is configured to communicate with the electronic system via a memory-sharing auxiliary bus. An arbiter is configured to arbitrate among the main interface, the memory-sharing auxiliary interface, a primary memory, and a secondary memory. Accordingly, the electronic system is capable of sharing either the primary memory or the secondary memory via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus, and the embedded memory system is capable of sharing a system memory of the electronic system via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus.

Abstract translation: 公开了一种嵌入式存储器系统。 主界面被配置为经由主总线与电子系统进行通信。 存储器共享辅助接口被配置为经由存储器共享辅助总线与电子系统通信。 仲裁器被配置为在主界面，存储器共享辅助接口，主存储器和辅助存储器之间进行仲裁。 因此，电子系统能够经由存储器共享辅助接口和存储器共享辅助总线共享主存储器或辅助存储器，并且嵌入式存储器系统能够经由该存储器共享辅助总线共享电子系统的系统存储器 内存共享辅助接口和内存共享辅助总线。

公开(公告)号：US20100030933A1

公开(公告)日：2010-02-04

申请号：US12183229

申请日：2008-07-31

Applicant: Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

Inventor： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC: G06F13/12 ,  G06F12/02

CPC classification number: G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract translation: 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。

公开(公告)号：US20090283600A1

公开(公告)日：2009-11-19

申请号：US12285187

申请日：2008-09-30

Applicant: Wen-Lin Chang ,  Satoshi Sugawa ,  Chuang Cheng ,  Ching-Hu Chen

Inventor： Wen-Lin Chang ,  Satoshi Sugawa ,  Chuang Cheng ,  Ching-Hu Chen

IPC: G06K7/06

CPC classification number: G06F13/385 ,  G06F13/4072

Abstract: A card reader includes a card interface, and one of the pins of the card interface is selected to decide the state of the card interface. The card reader further includes a control circuit to detect the logic state of the selected pin. If the logic state is a first one, the control circuit decides the card interface is enabled; otherwise, if the logic state is a second one, the control circuit decides the card interface is disabled. In some embodiments, a switch is connected between the selected pin and a power supply or a ground terminal, to be switched by a control signal to enable or disable the card interface.

Abstract translation: 读卡器包括卡接口，并且选择卡接口的一个引脚来决定卡接口的状态。 读卡器还包括用于检测所选引脚的逻辑状态的控制电路。 如果逻辑状态是第一个，控制电路决定卡接口被使能; 否则，如果逻辑状态是第二个逻辑状态，则控制电路决定卡接口被禁用。 在一些实施例中，开关连接在所选择的引脚和电源或接地端子之间，以通过控制信号切换以启用或禁用卡接口。

公开(公告)号：US4827243A

公开(公告)日：1989-05-02

申请号：US124487

申请日：1987-11-23

Applicant: Sheng-chuang Cheng

Inventor： Sheng-chuang Cheng

IPC: H01H13/06 ,  H01H13/70 ,  H01H3/14

CPC classification number: H01H13/70 ,  H01H13/063 ,  H01H2203/032 ,  H01H2205/002 ,  H01H2215/006 ,  H01H2221/042 ,  H01H2223/002 ,  H01H2233/036

Abstract: The present invention relates to a keyboard button structure. Each button has a pair of side mounted "U" shaped plates. Holes are provided in the housing panel and protrusions are formed inside the holes to permit rapid assembly of the button into the holes, and to prevent loss of buttons. A rubber member between the button and the panel provides button return and also permits feel of the contact and comfortable operation. The invention's novel structure provides economic and other advantages.

Abstract translation: 本发明涉及键盘按钮结构。 每个按钮都有一对侧面安装的“U”形板。 孔设置在壳体面板中，并且突出部形成在孔内部以允许按钮快速组装到孔中，并且防止按钮损失。 按钮和面板之间的橡胶构件提供按钮返回，并且还允许接触感和舒适的操作。 本发明的新颖结构提供了经济性和其他优点。