公开(公告)号：US20200334200A1

公开(公告)日：2020-10-22

申请号：US16869223

申请日：2020-05-07

Applicant: Intel Corporation

Inventor： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC: G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200327068A1

公开(公告)日：2020-10-15

申请号：US16831008

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Kiran C. Veernapu

IPC: G06F12/1045 ,  G06F12/1009 ,  G06T1/20 ,  G06T1/60 ,  G06F12/1027

Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline to bypass a memory access for the first virtual page based on the first page table entry, wherein the graphics pipeline is to read a field in the first page table entry to determine a value of the clear color.

公开(公告)号：US10803549B1

公开(公告)日：2020-10-13

申请号：US16450335

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Izajasz Piotr Wrosz ,  Tomasz Janczak ,  Prasoonkumar Surti

IPC: G06T15/04 ,  G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  G06T11/00 ,  G06T15/00

Abstract: Systems and methods for avoiding additional processing during generation of a procedural texture are disclosed. In one embodiment, a graphics processor includes memory to store graphics data and control data of a procedural texture. A texel shader dispatch circuitry is coupled to the memory. The texel shader dispatch circuitry is configured to maintain coherency between local memory of the texel shader dispatch circuitry during generation of the procedural texture via communication with the procedural texture to avoid overshading.

公开(公告)号：US10802970B1

公开(公告)日：2020-10-13

申请号：US16366266

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Altug Koker ,  Vidhya Krishnan ,  Ronald W. Silvas ,  John H. Feit ,  Prasoonkumar Surti ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F12/0837 ,  G06F9/38 ,  G06F16/907 ,  H04L9/06 ,  G06F12/0811

Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.

公开(公告)号：US20200311041A1

公开(公告)日：2020-10-01

申请号：US16371342

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Karol Szerszen ,  Eric Liskay ,  Karthik Vaidyanathan

IPC: G06F16/22 ,  G06N20/00 ,  G06T1/20

Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.

公开(公告)号：US20200301597A1

公开(公告)日：2020-09-24

申请号：US16358463

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Nilay Mistry

IPC: G06F3/06 ,  G06F12/06

Abstract: An apparatus to facilitate copying surface data is disclosed. The apparatus includes copy engine hardware to receive a command to access surface data from a source location in memory to a destination location in the memory, divide the surface data into a plurality of surface data sub-blocks, process the surface data sub-blocks to calculate virtual addresses to which accesses to the memory are to be performed and perform the memory accesses.

公开(公告)号：US10783084B2

公开(公告)日：2020-09-22

申请号：US16702073

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Atlug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0868 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0893 ,  G06F12/126 ,  G06T1/60

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200294301A1

公开(公告)日：2020-09-17

申请号：US16355364

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Arthur Hunter, JR. ,  Kamal Sinha ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma

IPC: G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06T17/20

Abstract: Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

公开(公告)号：US20200294182A1

公开(公告)日：2020-09-17

申请号：US16355573

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Varghese George ,  Altug Koker ,  Aravindh Anantaraman ,  Subramaniam Maiyuran ,  SungYe Kim ,  Valentin Andrei ,  Elmoustapha Ould-Ahmed-Vall ,  Joydeep Ray ,  Abhishek R. Appu ,  Nicolas C. Galoppo von Borries ,  Prasoonkumar Surti ,  Mike Macpherson

IPC: G06T1/20 ,  G06T1/60 ,  G06N20/00 ,  G06F16/17

Abstract: Apparatuses including general-purpose graphics processing units having on chip dense memory for temporal buffering are disclosed. In one embodiment, a graphics multiprocessor includes a plurality of compute engines to perform first computations to generate a first set of data, cache for storing data, and a high density memory that is integrated on chip with the plurality of compute engines and the cache. The high density memory to receive the first set of data, to temporarily store the first set of data, and to provide the first set of data to the cache during a first time period that is prior to a second time period when the plurality of compute engines will use the first set of data for second computations.

公开(公告)号：US20200241622A1

公开(公告)日：2020-07-30

申请号：US16782791

申请日：2020-02-05

Applicant: INTEL CORPORATION

Inventor： Abhishek R. Appu ,  Altug Koker ,  Eric J. Hoekstra ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Kamal Sinha ,  Balaji Vembu ,  Eric J. Asperheim ,  Sanjeev S. Jahagirdar ,  Joydeep Ray

IPC: G06F1/3225 ,  G06F1/3234

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.