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公开(公告)号：US20210232204A1
公开(公告)日：2021-07-29
申请号：US17108951
申请日：2020-12-01
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Kiran C. Veernapu , Eric J. Asperheim , Altug Koker , Balaji Vembu , Joydeep Ray , Abhishek R. Appu
IPC: G06F1/3234 , G06F9/46 , G06F1/329
Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20200150741A1
公开(公告)日：2020-05-14
申请号：US16661803
申请日：2019-10-23
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Kiran C. Veernapu , Eric J. Asperheim , Altug Koker , Balaji Vembu , Joydeep Ray , Abhishek R. Appu
IPC: G06F1/3234 , G06F1/329 , G06F9/46
Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10459509B2
公开(公告)日：2019-10-29
申请号：US15483580
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Kiran C. Veernapu , Eric J. Asperheim , Altug Koker , Balaji Vembu , Joydeep Ray , Abhishek R. Appu
IPC: G06F15/00 , G06F1/3234 , G06F1/329 , G06F9/46
Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20180307286A1
公开(公告)日：2018-10-25
申请号：US15493574
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Abhishek R. Appu , Joydeep Ray , Altug Koker , Prasoonkumar Surti , Kiran C. Veernapu
CPC classification number: G06F1/206 , G05B19/054 , G05B2219/15097
Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors, The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.
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公开(公告)号：US11320886B2
公开(公告)日：2022-05-03
申请号：US17108951
申请日：2020-12-01
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Kiran C. Veernapu , Eric J. Asperheim , Altug Koker , Balaji Vembu , Joydeep Ray , Abhishek R. Appu
IPC: G06F15/00 , G06F1/3234 , G06F9/46 , G06F1/329
Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US20200348897A1
公开(公告)日：2020-11-05
申请号：US16881262
申请日：2020-05-22
Applicant: Intel Corporation
Inventor： Eric J. Asperheim , Subramaniam M. Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC: G06F3/14 , G06F3/01 , G09G5/391 , G06F3/0484
Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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公开(公告)号：US20200210238A1
公开(公告)日：2020-07-02
申请号：US16726341
申请日：2019-12-24
Applicant: Intel Corporation
Inventor： Abhishek R Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10691392B2
公开(公告)日：2020-06-23
申请号：US15488758
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Eric J. Asperheim , Subramaniam M. Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC: G06F3/01 , G06F3/14 , G09G5/391 , G06F3/0484 , G09G5/00
Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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公开(公告)号：US20190265765A1
公开(公告)日：2019-08-29
申请号：US16286166
申请日：2019-02-26
Applicant: Intel Corporation
Inventor： Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Abhishek R. Appu , Joydeep Ray , Altug Koker , Prasoonkumar Surti , Kiran C. Veernapu
Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors. The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20240086138A1
公开(公告)日：2024-03-14
申请号：US18474361
申请日：2023-09-26
Applicant: Intel Corporation
Inventor： Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC: G06F3/14 , G06F3/01 , G06F3/0484 , G09G5/391
CPC classification number: G06F3/1438 , G06F3/013 , G06F3/0484 , G09G5/391 , G09G5/001 , G09G2340/0435 , G09G2352/00 , G09G2354/00 , G09G2360/08 , G09G2360/121
Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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