公开(公告)号：US20190064669A1

公开(公告)日：2019-02-28

申请号：US16126033

申请日：2018-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  H01L21/67 ,  G03F7/16 ,  H01L21/027 ,  G03F7/039 ,  H01L21/02

Abstract: The present disclosure provides a method that includes coating an edge portion of a wafer by a first chemical solution including a chemical mixture of an acid-labile group, a solubility control unit and a thermal acid generator; curing the first chemical solution to form a first protecting layer on the edge portion of the wafer; coating a resist layer on a front surface of the wafer; removing the first protecting layer by a first removing solution; and performing an exposing process to the resist layer.

公开(公告)号：US20190004430A1

公开(公告)日：2019-01-03

申请号：US15639033

申请日：2017-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui Weng ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/40

CPC classification number: G03F7/40 ,  G03F7/0392

Abstract: The present disclosure provides lithography resist materials and corresponding lithography techniques for improving lithography resolution, in particular, by reducing swelling of resist layers during development. An exemplary lithography method includes performing a treatment process on a resist layer to cause cross-linking of acid labile group components of the resist layer via cross-linkable functional components, performing an exposure process on the resist layer, and performing a development process on the resist layer. In some implementations, the resist layer includes an exposed portion and an unexposed portion after the exposure process, and the treatment process reduces solubility of the unexposed portion to a developer used during the development process by increasing a molecular weight of a polymer in the unexposed portion. The treatment process is performed before or after the exposure process. The treatment process can include performing a thermal treatment and/or an electromagnetic wave treatment to heat the resist layer.

公开(公告)号：US10162258B2

公开(公告)日：2018-12-25

申请号：US15381033

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsuan-Chen Chen ,  Chih-Cheng Lin ,  Hsin-Chang Lee ,  Yao-Ching Ku ,  Wei-Jen Lo ,  Anthony Yen ,  Chin-Hsiang Lin ,  Mark Chien

IPC: G03F1/24 ,  G03F1/62

Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

公开(公告)号：US20180337036A1

公开(公告)日：2018-11-22

申请号：US15597734

申请日：2017-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui Weng ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  G03F7/004 ,  G03F7/038

CPC classification number: H01L21/0274 ,  G03F7/0045 ,  G03F7/0382 ,  G03F7/162 ,  G03F7/168 ,  G03F7/2004 ,  G03F7/2006 ,  G03F7/2022 ,  G03F7/26 ,  H01L21/02057 ,  H01L21/30625 ,  H01L21/308

Abstract: The present disclosure provides a method for planarization. The method includes providing a substrate having a top surface and a trench recessed from the top surface; coating a sensitive material layer on the top surface of the substrate, wherein the sensitive material layer fills in the trench; performing an activation treatment to the sensitive material layer so that portions of the material layer are chemically changed; and performing a wet chemical process to the sensitive material layer so that top portions of the sensitive material layer above the trench are removed, wherein remaining portions of the sensitive material layer have top surfaces substantially coplanar with the top surface of the substrate.

公开(公告)号：US20180277359A1

公开(公告)日：2018-09-27

申请号：US15468109

申请日：2017-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Chin-Hsiang Lin ,  Ching-Yu Chang ,  Ming-Hui Weng

IPC: H01L21/027 ,  H01L21/311 ,  C09D201/06 ,  G03F7/11 ,  G03F7/16 ,  G03F7/09

Abstract: Under layer composition and methods of manufacturing semiconductor devices are disclosed. The method of manufacturing semiconductor device includes the following steps. A layer of an under layer composition is formed, wherein the under layer composition includes a polymeric material and a cross-linker, and the cross-linker includes at least one decomposable functional group. A curing process is performed on the layer of the under layer composition to form an under layer, wherein the cross-linker is crosslinked with the polymeric material to form a crosslinked polymeric material having the at least one decomposable functional group. A patterned photoresist layer is formed over the under layer. An etching process is performed to transfer a pattern of the patterned photoresist layer to the under layer. The under layer is removed by decomposing the decomposable functional group.

公开(公告)号：US10042252B2

公开(公告)日：2018-08-07

申请号：US15412856

申请日：2017-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hao Chen ,  Wei-Han Lai ,  Chien-Wei Wang ,  Chin-Hsiang Lin

IPC: G03F7/004 ,  G03F7/039 ,  G03F7/038 ,  G03F7/20 ,  G03F7/16 ,  G03F7/26 ,  G03F7/40 ,  H01L21/027 ,  G03F7/38 ,  C07C381/12

Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a polymer, a sensitizer, and a photo-acid generator (PAG), wherein the PAG includes a first phenyl ring and a second phenyl ring both chemically bonded to a sulfur, the first and second phenyl rings being further chemically bonded with enhanced sensitivity; performing an exposing process to the photoresist layer; and developing the photoresist layer, thereby forming a patterned photoresist layer.

公开(公告)号：US09449864B2

公开(公告)日：2016-09-20

申请号：US14494621

申请日：2014-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Ming Lin ,  Wan-Lai Chen ,  Chia-Hung Huang ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC: H01L21/683 ,  H01L21/68 ,  H01L21/268 ,  H01L23/544 ,  H01L21/67

CPC classification number: H01L21/681 ,  H01L21/268 ,  H01L21/67282 ,  H01L21/683 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system for orienting a semiconductor wafer. The system includes a wafer retaining device configured to retain a semiconductor wafer, a light source configured to emit light toward an edge exclusion area of the wafer, and a lens configured to direct and focus light emitted from the light source at a subsurface first part of a first portion of the wafer to alter a crystalline structure of the subsurface first part and form a subsurface mark that is detectable using light of a predetermined wavelength, a predetermined transmittance through the wafer, and at a predetermined reflectance angle relative to an axis of rotation of the wafer and based on the predetermined wavelength.

Abstract translation: 一种用于定向半导体晶片的系统。 该系统包括被配置为保持半导体晶片的晶片保持装置，被配置为朝向晶片的边缘排除区域发光的光源，以及被配置为将来自光源的光从第一部分 晶片的第一部分，以改变地下第一部分的晶体结构，并形成可使用预定波长的光，通过晶片的预定透射率和相对于旋转轴线的预定反射角可检测的地下标记 并且基于预定波长。

公开(公告)号：US09196515B2

公开(公告)日：2015-11-24

申请号：US14551302

申请日：2014-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

IPC: H01L21/67 ,  H01J37/317 ,  H01J37/32 ,  H01J37/16 ,  H01J37/20 ,  G03F7/16 ,  G03F7/30 ,  G03F7/20 ,  H01L21/677

CPC classification number: H01L21/67225 ,  G03F7/16 ,  G03F7/30 ,  G03F7/70991 ,  H01J37/16 ,  H01J37/20 ,  H01J37/3174 ,  H01J37/32899 ,  H01L21/67276 ,  H01L21/67745

Abstract: The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

Abstract translation: 本公开涉及一种用于半导体工件加工的平版印刷工具装置。 光刻工具装置将光刻工具组合成簇，并且将半导体工件在第一簇中的第一类型的多个光刻工具之间选择性地传输到第二簇中的第二类型的光刻工具。 通过转移组件实现选择性转移，转移组件耦合到识别第一类型的光刻工具中产生的缺陷的缺陷扫描工具。 所公开的平版印刷工具装置还利用共同的结构元件，例如壳体组件和诸如气体和化学品的共享功能元件。 光刻工具装置可以包括被配置成提供这些各种部件的模块化的烘烤，涂覆，曝光和显影单元，以便为给定的光刻制造工艺优化产量和效率。

公开(公告)号：US09158867B2

公开(公告)日：2015-10-13

申请号：US13647643

申请日：2012-10-09

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chun-Hsien Lin ,  Jui-Long Chen ,  Hui-Yun Chao ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC: G06F19/00 ,  G06F17/50 ,  G03F7/20

CPC classification number: G06F17/50 ,  G03F7/70533 ,  G03F7/70616 ,  G05B23/024

Abstract: A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.

Abstract translation: 一种用于分析半导体处理系统中的异常的方法，提供了在多个处理晶片中的每一个的多个处理步骤中的每一个处执行与多个工具中的每一个相关联的生产历史上的方差分析，并且关键处理步骤 确定。 执行在每个处理步骤对多个晶片的多个测量的回归分析，并且识别关键测量参数。 关键测量参数和关键过程步骤的协方差分析以及关键过程步骤基于f比进行排序，其中排列关键过程步骤的异常。 此外，与关键处理步骤中的每一个相关联的多个工具基于与协方差分析相关联的正交t比进行排序，其中对与关键处理步骤相关联的每个工具进行排序。