公开(公告)号：US20120223390A1

公开(公告)日：2012-09-06

申请号：US13147470

申请日：2011-06-24

Applicant: Renrong Liang ,  Ning Cui ,  Jing Wang ,  Jun Xu

Inventor： Renrong Liang ,  Ning Cui ,  Jing Wang ,  Jun Xu

IPC: H01L27/092 ,  H01L21/336 ,  H01L29/772

CPC classification number: H01L29/7391 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/66356

Abstract: The present disclosure provides a TFET, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; a gate stack formed on the channel region, wherein the gate stack comprises: a gate dielectric layer, and at least a first gate electrode and a second gate electrode distributed in a direction from the source region to the drain region and formed on the gate dielectric layer, and the first gate electrode and the second gate electrode have different work functions; and a first side wall and a second side wall formed on a side of the first gate electrode and on a side of the second gate electrode respectively.

Abstract translation: 本公开提供了一种TFET，其包括：基板; 形成在所述衬底中的沟道区，以及形成在所述沟道区的两侧的源极区和漏极区; 形成在所述沟道区上的栅极叠层，其中所述栅极堆叠包括：栅极电介质层，以及至少第一栅极电极和第二栅极电极，所述栅极电极和第二栅极电极沿着从所述源极区域到所述漏极区域的方向分布并形成在所述栅极电介质上 第一栅电极和第二栅电极具有不同的功函数; 以及分别形成在第一栅电极的一侧和第二栅极侧的第一侧壁和第二侧壁。

公开(公告)号：US08258572B2

公开(公告)日：2012-09-04

申请号：US12890132

申请日：2010-09-24

Applicant: Jhon-Jhy Liaw

Inventor： Jhon-Jhy Liaw

IPC: H01L29/772

CPC classification number: H01L27/11 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/785

Abstract: A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor.

Abstract translation: 静态随机存取存储器（SRAM）单元包括与直翅片物理断开的直翅片和弯曲的翅片。 弯曲的翅片具有平行于直翅片的第一部分和第二部分。 弯曲翅片的第一部分和直翅片之间的距离小于弯曲翅片的第二部分和直翅片之间的距离。 SRAM单元包括下拉晶体管，其包括第一栅极条的一部分，其分别与直鳍和弯曲鳍的第一部分形成第一和第二子下拉晶体管。 SRAM单元还包括一个包括第二栅极条的一部分的通过栅极晶体管，其形成具有直的鳍的第一子栅极晶体管。 下拉晶体管包括比传输栅极晶体管更多的鳍片。

公开(公告)号：US20120217555A1

公开(公告)日：2012-08-30

申请号：US13357381

申请日：2012-01-24

Applicant: Wataru SAITO ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

Inventor： Wataru SAITO ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC: H01L29/772

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7395

Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.

Abstract translation: 实施例的第一半导体器件包括第一导电类型的第一半导体层，第一控制电极，引出电极，第二控制电极和第三控制电极。 第一控制电极通过第一绝缘膜面对第一导电类型的第二半导体层，第二导电类型的第三半导体层和第一导电类型的第四半导体层。 第二控制电极和第三控制电极通过第二绝缘膜电连接到引出电极，并且与提取电极下方的第二半导体层相对。 第二控制电极和整个第三控制电极的至少一部分设置在引出电极的下方。 第二控制电极的电阻高于第三控制电极的电阻。

公开(公告)号：US20120211761A1

公开(公告)日：2012-08-23

申请号：US13315682

申请日：2011-12-09

Applicant: Atsushi YAMADA

Inventor： Atsushi YAMADA

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4903 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device includes: a semiconductor layer disposed above a substrate; an insulating film formed by oxidizing a portion of the semiconductor layer; and an electrode disposed on the insulating film, wherein the insulating film includes gallium oxide, or gallium oxide and indium oxide.

Abstract translation: 半导体器件包括：设置在衬底上方的半导体层; 通过氧化半导体层的一部分而形成的绝缘膜; 以及设置在所述绝缘膜上的电极，其中所述绝缘膜包括氧化镓，或氧化镓和氧化铟。

公开(公告)号：US20120211760A1

公开(公告)日：2012-08-23

申请号：US13308686

申请日：2011-12-01

Applicant: Atsushi Yamada

Inventor： Atsushi Yamada

IPC: H01L29/20 ,  H01L21/335 ,  H01L29/772

CPC classification number: H01L29/66462 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/56 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7787 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer.

Abstract translation: 半导体器件包括：氮化物半导体堆叠结构，包括载流子迁移层和载流子供给层; 设置在氮化物半导体层叠结构上并包括有源区和非活性区的p型氮化物半导体层; 设置在p型氮化物半导体层中的非活性区域上的n型氮化物半导体层; 以及设置在p型氮化物半导体层的有源区上的栅电极。

公开(公告)号：US08247870B2

公开(公告)日：2012-08-21

申请号：US11903879

申请日：2007-09-25

Applicant: Jungcheng Kao ,  Luming Guo

Inventor： Jungcheng Kao ,  Luming Guo

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/66659 ,  G09G3/3406 ,  H01L27/088 ,  H01L29/42368 ,  H01L29/7835

Abstract: A method for integration is disclosed herein. The method includes forming an N-type double drain (NDD) layer, and fabricating at least one transistor from a controller circuitry and a transistor switch on a single chip. The controller circuitry is operable for controlling the transistor switch.

Abstract translation: 本文公开了一种用于集成的方法。 该方法包括形成N型双漏极（NDD）层，并且在单个芯片上从控制器电路和晶体管开关制造至少一个晶体管。 控制器电路可操作用于控制晶体管开关。

公开(公告)号：US20120193713A1

公开(公告)日：2012-08-02

申请号：US13017966

申请日：2011-01-31

Applicant: Pranita Kulkarni ,  Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam Shahidi ,  Hemanth Jagannathan

Inventor： Pranita Kulkarni ,  Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Ghavam Shahidi ,  Hemanth Jagannathan

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/66803 ,  H01L29/41791 ,  H01L29/785

Abstract: A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each is second spacer adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.

Abstract translation: 形成具有减小的电容，存取电阻和接触电阻的鳍状场效应晶体管（finFET）器件。 提供掩埋氧化物，鳍状物，栅极和第一间隔物。 该鳍被掺杂以形成在栅极下方延伸的延伸结。 第二间隔件形成在延伸接头的顶部。 每个是与栅极的任一侧相邻的第一间隔件之间的第二间隔件。 延伸结和未被栅极保护的埋入氧化物，第一间隔物和第二间隔物被回蚀刻以产生空隙。 空隙填充有半导体材料，使得半导体材料的顶表面延伸到延伸接头的顶表面之下，以形成凹陷的源极 - 漏极区域。 在凹陷的源极 - 漏极区域，延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。

公开(公告)号：US20120193687A1

公开(公告)日：2012-08-02

申请号：US13017127

申请日：2011-01-31

Applicant: Jeehwan Kim ,  Jin-Hong Park ,  Devendra Sadana ,  Kuen-Ting Shiu

Inventor： Jeehwan Kim ,  Jin-Hong Park ,  Devendra Sadana ,  Kuen-Ting Shiu

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L29/20 ,  H01L21/26513 ,  H01L21/28575 ,  H01L29/0847 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/78

Abstract: Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor.

Abstract translation: 本发明的实施例提供一种制造电接触的方法。 该方法包括提供化合物III-V族半导体材料的衬底，其具有与衬底的表面相邻的至少一个导电掺杂区域。 该方法还包括通过在衬底的表面上沉积锗的单晶层以至少部分地覆盖在至少一个导电掺杂区域上来将至少一个导电掺杂区域的电接触制造到该至少一个导电掺杂区域， 通过注入掺杂剂，在非晶锗层的暴露表面上形成金属层，并对具有上层金属层的非晶锗层进行金属诱导结晶（MIC）工艺，将锗的晶体层分解成无定形锗层， 将无定形锗层转化为结晶锗层并激活注入的掺杂剂。 电接触可以是晶体管的源极或漏极接触。

公开(公告)号：US08232604B2

公开(公告)日：2012-07-31

申请号：US12113510

申请日：2008-05-01

Applicant: Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

Inventor： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/772

CPC classification number: H01L21/84 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66772 ,  H01L29/78654

Abstract: A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

Abstract translation: 提供晶体管，其包括包括源极区和漏极区的硅层，设置在源极区域和漏极区域之间的硅层上的栅极堆叠以及设置在栅极堆叠的侧壁上的侧壁间隔物。 栅堆叠包括第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。 侧壁间隔件包括高介电常数材料并且覆盖至少栅极叠层的第二和第三层的侧壁。 还提供了制造这种晶体管的方法。

公开(公告)号：US20120187491A1

公开(公告)日：2012-07-26

申请号：US13429948

申请日：2012-03-26

Applicant: Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

IPC: H01L29/772

CPC classification number: H01L21/187 ,  H01L21/6835 ,  H01L21/84 ,  H01L27/12 ,  H01L29/1083 ,  H01L2221/6835 ,  H01L2221/68368

Abstract: A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.

Abstract translation: 提供一种形成电气装置的方法，包括在SOI衬底的第一半导体层上形成至少一个半导体器件。 形成接触至少一个半导体器件和第一半导体层的处理结构。 去除第二半导体层和SOI衬底的电介质层的至少一部分以提供第一半导体层的基本暴露的表面。 可以通过将掺杂剂通过第一半导体层的基本上暴露的表面注入从半导体层的基本暴露的表面延伸的半导体层的第一厚度来形成退化的阱，其中半导体层的剩余厚度基本上不含 的回归井掺杂剂。 退火井可以进行激光退火。