公开(公告)号：US20210082832A1

公开(公告)日：2021-03-18

申请号：US16573817

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Min-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.

公开(公告)号：US10651279B2

公开(公告)日：2020-05-12

申请号：US16227592

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Ching-Fu Yeh ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L29/16 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.

公开(公告)号：US10269915B2

公开(公告)日：2019-04-23

申请号：US15615901

申请日：2017-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Yung-Chih Wang ,  Shin-Yi Yang ,  Chih-Wei Lu ,  Hsin-Ping Chen ,  Shau-Lin Shue

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/43 ,  H01L29/12 ,  H01L29/06 ,  H01L21/768

Abstract: A vertical MOS transistor includes a substrate, a metal line disposed on the substrate, a semiconductor pillar disposed on and in contact with the metal line, a gate dielectric layer disposed surrounding the semiconductor pillar, a metal gate disposed surrounding a portion of the semiconductor pillar, and a gate electrode disposed in contact with the metal gate. In some embodiments, a width of an end of the gate electrode in contact with the metal gate is narrower than a width of an end of the gate electrode away from the metal gate.

公开(公告)号：US09728485B1

公开(公告)日：2017-08-08

申请号：US15016886

申请日：2016-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/373 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/3736 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the dielectric layer, and the conductive feature includes a catalyst layer and a conductive element. The catalyst layer is between the conductive element and the dielectric layer, and the catalyst layer is in physical contact with the conductive element. The catalyst layer continuously surrounds a sidewall and a bottom of the conductive element. The catalyst layer is made of a material different from that of the conductive element, and the catalyst layer is capable of lowering a formation temperature of the conductive element.