公开(公告)号：US20210160481A1

公开(公告)日：2021-05-27

申请号：US17103415

申请日：2020-11-24

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Chun-Chi Chen ,  Adarsh Krishnan Ramasubramonian ,  Vadim Seregin ,  Wei-Jung Chien ,  Geert Van der Auwera ,  Marta Karczewicz

IPC: H04N19/105 ,  H04N19/61 ,  H04N19/186 ,  H04N19/176

Abstract: A video decoder can be configured to determine that a block of the video data is encoded using an adaptive color transform (ACT); determine that the block is encoded in a joint chroma mode, wherein for the joint chroma mode a single chroma residual block is encoded for a first chroma component of the block and a second chroma component of the block; determine a quantization parameter (QP) for the block; determine an ACT quantization parameter (QP) offset for the block based on the block being encoded using the ACT and encoded in the joint chroma mode; and determine an ACT QP for the block based on the QP and the ACT QP offset.

公开(公告)号：US11019360B2

公开(公告)日：2021-05-25

申请号：US16824431

申请日：2020-03-19

Applicant: QUALCOMM Incorporated

Inventor： Adarsh Krishnan Ramasubramonian ,  Geert Van der Auwera ,  Luong Pham Van ,  Marta Karczewicz

IPC: H04N19/593 ,  H04N19/176 ,  H04N19/70 ,  H04N19/105

Abstract: In some examples, a device includes a memory configured to store a current block of the video data and one or more processors coupled to the memory. The one or more processors may be configured to derive a reference sample position (RSP) for a current sample of a current block according to one or more RSP derivation models. The one or more RSP derivation models may include a circular model, an elliptical model, a piece-wise linear model, a table-based model, or a parametric model. The one or more processors may be further configured to determine a reference sample value for a reference sample at the RSP, determine a predicted value for the current sample using the reference sample value, and code the current sample using the predicted value.

公开(公告)号：US20210152841A1

公开(公告)日：2021-05-20

申请号：US17096740

申请日：2020-11-12

Applicant: QUALCOMM Incorporated

Inventor： Nan Hu ,  Vadim Seregin ,  Cheng-Teh Hsieh ,  Marta Karczewicz

IPC: H04N19/44 ,  H04N19/105 ,  H04N19/132 ,  H04N19/117 ,  H04N19/82 ,  H04N19/186 ,  H04N19/176

Abstract: An example device for decoding video data includes one or more processors implemented in circuitry and configured to: decode a coding tree unit (CTU) of video data, the CTU including a luminance (luma) block and a chrominance (chroma) block, to produce a decoded luma block and a decoded chroma block; determine that a chroma sample of the decoded chroma block is on a first side of an adaptive loop filter (ALF) virtual boundary and that a co-located luma sample of the decoded luma block is on a second side of the ALF virtual boundary, the co-located luma sample being co-located with the chroma sample, the first side being different than the second side; and in response to determining that the chroma sample is on the first side and the luma sample is on the second side, disable cross-component adaptive loop filtering (CC-ALF) for the chroma sample.

公开(公告)号：US20210136422A1

公开(公告)日：2021-05-06

申请号：US17084119

申请日：2020-10-29

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/96 ,  H04N19/119 ,  H04N19/176 ,  H04N19/70 ,  H04N19/172 ,  H04N5/232 ,  H04N5/765 ,  H04N5/917

Abstract: A video encoder may encode a picture of video data using merge estimation regions (MERs). The video encoder may determine merge candidate lists in parallel for coding units within a MER. The video encoder may also partition the picture of video data into coding units according to a constraint, wherein the constraint specifies that the partitioning is constrained such that, for each MER containing one or more coding units, the one or more coding units are completely in the MER, and for each coding unit containing one or more MERs, the MERs are completely in the coding unit.

公开(公告)号：US20210127137A1

公开(公告)日：2021-04-29

申请号：US17077587

申请日：2020-10-22

Applicant: QUALCOMM Incorporated

Inventor： Hilmi Enes Egilmez ,  Amir Said ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/70 ,  H04N19/176 ,  H04N19/60 ,  H04N19/18

Abstract: A video decoder can be configured to receive, in a syntax structure that applies to a current block, graph-related information; determine a transform matrix based on the received graph-related syntax information; perform an inverse transform based on the determined transform matrix of one or more coefficient values to generate a residual block; and reconstruct the current block of the video data based on the residual block.

公开(公告)号：US20210092449A1

公开(公告)日：2021-03-25

申请号：US17022253

申请日：2020-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yao-Jen Chang ,  Vadim Seregin ,  Muhammed Zeyd Coban ,  Marta Karczewicz

IPC: H04N19/70 ,  H04N19/172

Abstract: An example device includes a memory and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine a value of a first syntax element indicative of a number of subpictures in a picture of video data. The one or more processors are configured to determine, for each subpicture among the subpictures in the picture, a value of a respective second syntax element indicative of an identification of a respective subpicture. The one or more processors are also configured to code the respective subpicture identified by the respective second syntax element.

公开(公告)号：US20210092405A1

公开(公告)日：2021-03-25

申请号：US17024522

申请日：2020-09-17

Applicant: QUALCOMM Incorporated

Inventor： Thibaud Laurent Biatek ,  Adarsh Krishnan Ramasubramonian ,  Geert Van der Auwera ,  Marta Karczewicz

IPC: H04N19/159 ,  H04N19/46 ,  H04N19/176 ,  H04N19/70 ,  H04N19/59

Abstract: A video decoder obtains a transpose flag from the bitstream. The video decoder determines an input vector based on neighboring samples for a current block of the video data. The transpose flag indicates whether the input vector is transposed. Additionally, the video decoder determines a prediction signal. Determining the prediction signal includes multiplying a MIP matrix by the input vector. The prediction signal includes values corresponding to a first set of locations in a prediction block for the current block and the MIP matrix corresponds to the MIP mode index. The video decoder applies an interpolation process to the prediction signal to determine values corresponding to a second set of locations in the prediction block for the current block.

公开(公告)号：US20210092376A1

公开(公告)日：2021-03-25

申请号：US17028492

申请日：2020-09-22

Applicant: QUALCOMM Incorporated

Inventor： Alican Nalci ,  Hilmi Enes Egilmez ,  Yung-Hsuan Chao ,  Muhammed Zeyd Coban ,  Hongtao Wang ,  Marta Karczewicz

IPC: H04N19/119 ,  H04N19/46 ,  H04N19/176 ,  H04N19/103 ,  H04N19/18

Abstract: A video decoder may be configured to determine whether a block of video data is to be further partitioned based on the size of the block of video data and a lossless coding flag. A video decoder may decode a lossless coding flag for a block of video data, wherein the block of video data is in a picture that includes both lossy coded blocks and lossless coded blocks, determine that the lossless coding flag indicates a lossless coding mode for the block, and partition the block into sub-blocks based on a size of the block and the determination of the lossless coding mode.

公开(公告)号：US10958900B2

公开(公告)日：2021-03-23

申请号：US16705174

申请日：2019-12-05

Applicant: QUALCOMM Incorporated

Inventor： Yung-Hsuan Chao ,  Dmytro Rusanovskyy ,  Yu Han ,  Wei-Jung Chien ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/159 ,  H04N19/137

Abstract: Embodiments include systems and methods of generating merge candidates for an inter-prediction mode of a video block. In particular, embodiments include methods of generating spatial-temporal motion vector predictor candidates. Embodiments may include video encoders and video decoders.

公开(公告)号：US20210084343A1

公开(公告)日：2021-03-18

申请号：US17024422

申请日：2020-09-17

Applicant: QUALCOMM Incorporated

Inventor： Adarsh Krishnan Ramasubramonian ,  Geert Van der Auwera ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/96 ,  H04N19/186

Abstract: An example device includes a memory and one or more processors. The one or more processors are configured to determine whether a first coding tree unit (CTU) is coded using single tree and based on the first CTU being coded using single tree, determine a first transform unit (TU) based on a first transform block (TB) of luma samples and a first two corresponding TBs of chroma samples. The one or more processors are also configured to determine whether a second CTU is coded using dual tree and based on the second CTU being coded using dual tree, determine a second TU based on either (i) a second TB of luma samples or (ii) a second two TBs of chroma samples. The first TU includes syntax structures used to transform first TB samples and the second TU includes syntax structures used to transform second TB samples.