公开(公告)号：US20200035005A1

公开(公告)日：2020-01-30

申请号：US16533920

申请日：2019-08-07

Applicant: Intel Corporation

Inventor： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  ElMoustapha Ould-Ahmed-Vall ,  James M. Holland

IPC: G06T11/60 ,  H04N19/124 ,  H04N19/167 ,  H04N19/17 ,  H04N19/436 ,  H04N19/503 ,  G06T9/00

Abstract: An embodiment of a graphics apparatus may include a focus identifier to identify a focus area, and a color compressor to selectively compress color data based on the identified focus area. Another embodiment of a graphics apparatus may include a motion detector to detect motion of a real object, a motion predictor to predict a motion of the real object, and an object placer to place a virtual object relative to the real object based on the predicted motion of the real object. Another embodiment of a graphics apparatus may include a frame divider to divide a frame into viewports, a viewport prioritizer to prioritize the viewports, a renderer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter to transmit a completed rendered viewport. Other embodiments are disclosed and claimed.

公开(公告)号：US20200027192A1

公开(公告)日：2020-01-23

申请号：US16531713

申请日：2019-08-05

Applicant: Intel Corporation

Inventor： Kiran C. Veernapu ,  Mohammed Tameem ,  Altug Koker ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F12/02 ,  G06F12/0875

Abstract: A mechanism is described for facilitating dynamic cache allocation in computing devices in computing devices. A method of embodiments, as described herein, includes facilitating monitoring one or more bandwidth consumptions of one or more clients accessing a cache associated with a processor; computing one or more bandwidth requirements of the one or more clients based on the one or more bandwidth consumptions; and allocating one or more portions of the cache to the one or more clients in accordance with the one or more bandwidth requirements.

公开(公告)号：US20200026514A1

公开(公告)日：2020-01-23

申请号：US16526147

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kamal Sinha ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  David Puffer ,  Supratim Pal ,  Eric J. Hoekstra ,  Travis T. Schluessler ,  Linda L. Hurd

IPC: G06F9/30 ,  G06F9/38 ,  G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F9/46 ,  G09G5/36

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

公开(公告)号：US10521349B2

公开(公告)日：2019-12-31

申请号：US16277267

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Prasoonkumar Surti ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Abhishek R. Appu ,  Nicolas C. Galoppo Von Borries ,  Joydeep Ray ,  Narayan Srinivasa ,  Feng Chen ,  Ben J. Ashbaugh ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0837 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20 ,  G06F12/0815 ,  G06N3/04 ,  G06N3/063

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

公开(公告)号：US10482562B2

公开(公告)日：2019-11-19

申请号：US15493522

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker ,  Bryan R. White ,  David J. Cowperthwaite ,  Joydeep Ray ,  Murali Ramadoss

IPC: G06F15/80 ,  G06T1/20 ,  G06F9/50 ,  G06F9/455

Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.

公开(公告)号：US10452552B2

公开(公告)日：2019-10-22

申请号：US15488988

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0855 ,  G06F9/38 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

公开(公告)号：US10452397B2

公开(公告)日：2019-10-22

申请号：US15477022

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Abhishek R. Appu ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu

IPC: G06F9/30 ,  G06F12/0842 ,  G09G5/393 ,  G06T1/60 ,  G06T1/20 ,  G06F9/50

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first number of threads to be scheduled for each context of a plurality of contexts in a multi-context processing system, allocate a second number of streaming multiprocessors (SMs) to the respective plurality of contexts, and dispatch threads from the plurality of contexts only to the streaming multiprocessor(s) allocated to the respective plurality of contexts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190317899A1

公开(公告)日：2019-10-17

申请号：US16394829

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu ,  Vasanth Ranganathan

IPC: G06F12/0842 ,  G06F12/0831 ,  G06F12/0811 ,  G06T1/60

Abstract: A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).

公开(公告)号：US10430990B2

公开(公告)日：2019-10-01

申请号：US15710828

申请日：2017-09-20

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge Garcia Pabon ,  Vasanth Ranganathan ,  Saikat Mandal ,  Karol Szerszen ,  Luis Cruz Camacho ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G09G5/00 ,  G06T9/00

Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.

公开(公告)号：US10401954B2

公开(公告)日：2019-09-03

申请号：US15488666

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  James M. Holland ,  Pattabhiraman K ,  Sayan Lahiri ,  Radhakrishnan Venkataraman ,  Kamal Sinha ,  Ankur N. Shah ,  Deepak S. Vembar ,  Abhishek R. Appu ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T7/80 ,  G06F3/0481 ,  G06F3/01 ,  G06F3/16 ,  G06T1/60 ,  G06T3/40 ,  G06F3/147 ,  G06T15/00 ,  G06T19/00

Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.