公开(公告)号：US20230300368A1

公开(公告)日：2023-09-21

申请号：US18304964

申请日：2023-04-21

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Jianle Chen ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/52 ,  H04N19/70 ,  H04N19/176 ,  H04N19/132 ,  H04N19/46

CPC classification number: H04N19/52 ,  H04N19/132 ,  H04N19/176 ,  H04N19/46 ,  H04N19/70

Abstract: An example method includes encoding, in a video bitstream, a first syntax element specifying whether affine model based motion compensation is enabled; based on affine model based motion compensation being enabled, encoding, in the video bitstream, a second syntax element specifying a maximum number of subblock-based merging motion vector prediction candidates, wherein a value of the second syntax element is constrained based on a value other than a value of the first syntax element; and encoding a picture of the video data based on the maximum number of subblock-based merging motion vector prediction candidates.

公开(公告)号：US11611759B2

公开(公告)日：2023-03-21

申请号：US16879462

申请日：2020-05-20

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Wei-Jung Chien ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/159 ,  H04N19/70 ,  H04N19/119 ,  H04N19/139

Abstract: An example device for coding video data determines for a first block of the video data whether to use a sub-block merge mode. Based on the determination not to use the sub-block merge mode for the first block, the device determines whether to use a merge mode with blending for the first block. Based on the determination to use the merge mode with blending for the first block, the device codes the first block with the merge mode with blending.

公开(公告)号：US20220329844A1

公开(公告)日：2022-10-13

申请号：US17809160

申请日：2022-06-27

Applicant: QUALCOMM Incorporated

Inventor： Luong Pham Van ,  Wei-Jung Chien ,  Vadim Seregin ,  Marta Karczewicz ,  Han Huang

IPC: H04N19/52 ,  H04N19/15 ,  H04N19/615 ,  H04N19/513

Abstract: An example device for coding video data includes a memory configured to store video data; and one or more processing units implemented in circuitry and configured to: store motion information for a first coding tree unit (CTU) line of a picture in a first history motion vector predictor (MVP) buffer of the memory; reset a second history MVP buffer of the memory; and after resetting the second history MVP buffer, store motion information for a second CTU line of the picture in the second history MVP buffer, the second CTU line being different than the first CTU line. Separate threads of a video coding process executed by the one or more processors may process respective CTU lines, in some examples.

公开(公告)号：US20220201322A1

公开(公告)日：2022-06-23

申请号：US17644519

申请日：2021-12-15

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Kevin Pascal Andre Reuze ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/44 ,  H04N19/176 ,  H04N19/159 ,  H04N19/137

Abstract: An example device for decoding video data includes one or more processors configured to: determine that a first weight and a second weight are specified for a bi-prediction mode predicted current block of video data; determine whether the current block is to be predicted using multi-hypothesis prediction (MHP) mode with the bi-prediction mode as a base mode; in response to determining that the current block is to be predicted using the MHP mode with the bi-prediction mode as the base mode, determine an additional inter-prediction mode of the MHP mode; generate a first prediction block according to the bi-prediction mode; generate a second prediction block according to the additional inter-prediction mode; generate a final prediction block for the current block according to the MHP mode using the first prediction block and the second prediction block; and decode the current block using the final prediction block.

公开(公告)号：US20220201315A1

公开(公告)日：2022-06-23

申请号：US17556142

申请日：2021-12-20

Applicant: QUALCOMM Incorporated

Inventor： Zhi Zhang ,  Han Huang ,  Chun-Chi Chen ,  Yan Zhang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/139 ,  H04N19/176 ,  H04N19/157 ,  H04N19/186 ,  H04N19/132 ,  H04N19/513

Abstract: Example devices and techniques for multi-pass decoder-side motion vector refinement (DMVR) are disclosed. An example device includes memory configured to store video data and one or more processors coupled to the memory. The one or more processors are configured to apply a multi-pass DMVR to a motion vector for a block of the video data to determine at least one refined motion vector and decode the block based on the at least one refined motion vector. The multi-pass DMVR includes a block-based first pass, a sub-block-based second pass, and a sub-block-based third pass.

公开(公告)号：US11336900B2

公开(公告)日：2022-05-17

申请号：US16912657

申请日：2020-06-25

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/159 ,  H04N19/105 ,  H04N19/147 ,  H04N19/176

Abstract: Embodiments include methods and apparatus for encoding and decoding video data. In particular, embodiments include methods and apparatus for encoding and decoding video using a combined inter/intra prediction mode. In one such embodiment, the inter prediction is performed using a equal weighted bi-prediction mode determined using a merge mode that would otherwise indicate a non-equal weighted bi-prediction.

公开(公告)号：US11310519B2

公开(公告)日：2022-04-19

申请号：US17022700

申请日：2020-09-16

Applicant: QUALCOMM Incorporated

Inventor： Bappaditya Ray ,  Han Huang ,  Geert Van der Auwera ,  Marta Karczewicz

IPC: H04N19/51 ,  H04N19/117 ,  H04N19/176

Abstract: An example device for decoding video data includes memory configured to store the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine whether a coding mode for a current block of the video data is an affine mode. The one or more processors are also configured to determine whether pattern refined optical flow (PROF) is enabled in the sequence parameter set (SPS) for the current block. Based at least in part on the coding mode for the current block being the affine mode and PROF being enabled in the SPS for the current block, the one or more processors are configured to disable a deblocking filter for subblock boundaries of the current block and decode the current block with the deblocking filter disabled for the subblock boundaries of the current block.

公开(公告)号：US20210314598A1

公开(公告)日：2021-10-07

申请号：US17222380

申请日：2021-04-05

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Jianle Chen ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/52 ,  H04N19/70 ,  H04N19/46 ,  H04N19/132 ,  H04N19/176

Abstract: An example method includes encoding, in a video bitstream, a first syntax element specifying whether affine model based motion compensation is enabled; based on affine model based motion compensation being enabled, encoding, in the video bitstream, a second syntax element specifying a maximum number of subblock-based merging motion vector prediction candidates, wherein a value of the second syntax element is constrained based on a value other than a value of the first syntax element; and encoding a picture of the video data based on the maximum number of subblock-based merging motion vector prediction candidates.

公开(公告)号：US20210314567A1

公开(公告)日：2021-10-07

申请号：US17220546

申请日：2021-04-01

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Jianle Chen ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/119 ,  H04N19/96 ,  H04N19/186 ,  H04N19/176

Abstract: A video encoder and video decoder are configured to determine a partitioning for a picture of video data based on a virtual pipeline data unit (VPDU) size. For example, the video encoder and video decoder may determine a maximum ternary tree size to be in the range of a minimum allowed block size to a minimum of the VPDU size and a maximum coding tree unit (CTU) size, and/or determine a minimum quadtree size to be in the range of a minimum allowed block size to a minimum of the VPDU size and the maximum CTU size.

公开(公告)号：US11089328B2

公开(公告)日：2021-08-10

申请号：US16858046

申请日：2020-04-24

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/577 ,  H04N19/169 ,  H04N19/159 ,  H04N19/176

Abstract: A video coder is configured to code a block of video data using bi-prediction with bi-directional optical flow. The video coder may determine an offset using bi-directional optical flow and may add the offset to prediction samples determined from the bi-prediction. In one example, the video coder code a current block of video data using bi-prediction and bi-directional optical flow, wherein the bi-directional flow does not include one or more of a rounding operation or a division by 2 in an offset calculation. Additionally, the video coder may perform a motion vector refinement calculation for the bi-directional flow, wherein the motion vector refinement calculation is compensated to account for the offset calculation not including the division by 2.