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    Semiconductor device including multiple inner spacers with different etch rates and method of making
    101.
    发明授权
    Semiconductor device including multiple inner spacers with different etch rates and method of making 有权

    公开(公告)号：US12249639B2

    公开(公告)日：2025-03-11

    申请号：US18401833

    申请日：2024-01-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786

    Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

    SEMICONDUCTOR DEVICE AND METHOD
    102.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD 有权

    公开(公告)号：US20250056832A1

    公开(公告)日：2025-02-13

    申请号：US18932253

    申请日：2024-10-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

    IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

    Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AIW); and a fill material over the first work function tuning layer.

    Gate oxide of nanostructure transistor with increased corner thickness
    103.
    发明授权
    Gate oxide of nanostructure transistor with increased corner thickness 有权

    公开(公告)号：US12218197B2

    公开(公告)日：2025-02-04

    申请号：US18364995

    申请日：2023-08-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shu-Han Chen ,  Yi-Shao Li ,  Chun-Heng Chen ,  Chi On Chui

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

    Abstract: A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.

    SEMICONDUCTOR DEVICE AND METHOD
    104.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD 有权

    公开(公告)号：US20250006500A1

    公开(公告)日：2025-01-02

    申请号：US18762105

    申请日：2024-07-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui ,  Yung-Cheng Lu

    IPC: H01L21/28 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

    Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

    Semiconductor device and method
    107.
    发明授权
    Semiconductor device and method 有权

    公开(公告)号：US12166095B2

    公开(公告)日：2024-12-10

    申请号：US18525521

    申请日：2023-11-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

    IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

    Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.

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