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    Loop filter padding for 360-degree video coding
    101.
    发明授权
    Loop filter padding for 360-degree video coding 有权

    公开(公告)号：US11212438B2

    公开(公告)日：2021-12-28

    申请号：US16270275

    申请日：2019-02-07

    Applicant: QUALCOMM Incorporated

    Inventor： Geert Van der Auwera ,  Muhammed Zeyd Coban ,  Fnu Hendry ,  Marta Karczewicz

    IPC: H04N19/597 ,  H04N19/82 ,  H04N19/503 ,  H04N19/86 ,  H04N5/232 ,  H04N19/46 ,  H04N19/167 ,  H04N19/33

    Abstract: An example method includes, receiving an encoded picture of 360-degree video data, the encoded picture of 360-degree video data being arranged in packed faces obtained from a projection of a sphere of the 360-degree video data; decoding the picture of encoded 360-degree video data to obtain a reconstructed picture of 360-degree video data, the reconstructed picture of 360-degree video data being arranged in the packed faces; padding the reconstructed picture of 360-degree video data to generate a padded reconstructed picture of 360-degree video data; in-loop filtering the padded reconstructed picture of 360-degree video data to generate a padded and filtered reconstructed picture of 360-degree video data; and storing the padded and filtered reconstructed picture of 360-degree video data in a reference picture memory for use in predicting subsequent pictures of 360-degree video data.

    Grouped coding for palette syntax in video coding
    102.
    发明授权
    Grouped coding for palette syntax in video coding 有权

    公开(公告)号：US11202101B2

    公开(公告)日：2021-12-14

    申请号：US16815605

    申请日：2020-03-11

    Applicant: QUALCOMM Incorporated

    Inventor： Yung-Hsuan Chao ,  Marta Karczewicz

    IPC: H04N19/70 ,  H04N19/184 ,  H04N19/50

    Abstract: A video decoder may divide a current coding unit (CU) of video data into a plurality of index groups. The video decoder may decode syntax elements common to all of the index groups and then separately and sequentially decode syntax elements for each of the index groups. By first decoding the syntax elements used by all the index groups and then separately grouping the decoding of the syntax elements for the index groups, the video decoder may begin the construction process of some samples of the current CU without having to wait to complete decoding of all of the syntax elements of the current CU. As such, the techniques of this disclosure may decrease the amount of time required and/or the delay introduced by the decoding process.

    Transform unit design for video coding
    104.
    发明授权
    Transform unit design for video coding 有权

    公开(公告)号：US11184617B2

    公开(公告)日：2021-11-23

    申请号：US17025529

    申请日：2020-09-18

    Applicant: QUALCOMM Incorporated

    Inventor： Hilmi Enes Egilmez ,  Amir Said ,  Vadim Seregin ,  Marta Karczewicz

    IPC: H04N19/129 ,  H04N19/159 ,  H04N19/176

    Abstract: An example device for decoding video data includes a memory configured to store the video data and one or more processors coupled to the memory. The one or more processors are configured to reorganize 2-D dequantized coefficients according to a first ordering. The one or more processors are configured to apply an inverse low-frequency non-separable transform (LFNST) to the reorganized 2-D dequantized coefficients to create inverse transformed coefficients. The one or more processors are configured to reorganize the inverse transformed coefficients according to a second ordering, the second ordering being based on an array including values, wherein each value in the array corresponds to a position in a 2-D block and the values in the array denote indices of the 2-D block in a defined order. The one or more processors are configured to decode the video data based on the second ordered inverse transformed coefficients.

    Position dependent intra prediction combination with multiple reference lines for intra prediction
    105.
    发明授权
    Position dependent intra prediction combination with multiple reference lines for intra prediction 有权

    公开(公告)号：US11159806B2

    公开(公告)日：2021-10-26

    申请号：US16434113

    申请日：2019-06-06

    Applicant: QUALCOMM Incorporated

    Inventor： Adarsh Krishnan Ramasubramonian ,  Geert Van der Auwera ,  Marta Karczewicz

    IPC: H04N19/174 ,  H04N19/11 ,  H04N19/176 ,  H04N19/61 ,  H04N19/70

    Abstract: Techniques are described using Position Dependent Intra Prediction Combination (PDPC) and multiple reference lines. For example, a video coder (e.g., an encoder and/or decoder) can predict an initial prediction sample value for a sample of a current block using an intra-prediction mode. The initial prediction sample value can be predicted from a first neighboring block and/or a second neighboring block of the current block. One or more reference sample values can be determined from at least one line of multiple lines of reference samples from the first neighboring block and/or the second neighboring block. At least one of the lines from the multiple lines used for determining the reference sample value(s) is not adjacent to the current block. A final prediction sample value can be determined for the sample of the current block, such as by modifying the initial prediction sample value using the one or more reference sample values.

    LOW-FREQUENCY NON-SEPARABLE TRANSFORM INDEX SIGNALING IN VIDEO CODING
    106.
    发明申请
    LOW-FREQUENCY NON-SEPARABLE TRANSFORM INDEX SIGNALING IN VIDEO CODING 有权

    公开(公告)号：US20210321137A1

    公开(公告)日：2021-10-14

    申请号：US17214184

    申请日：2021-03-26

    Applicant: QUALCOMM Incorporated

    Inventor： Hilmi Enes Egilmez ,  Vadim Seregin ,  Marta Karczewicz

    IPC: H04N19/70 ,  H04N19/46 ,  H04N19/119 ,  H04N19/159 ,  H04N19/186 ,  H04N19/176

    Abstract: An example device for coding video data includes memory configured to store the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to parse or signal all luma coefficients of a block of the video data from or to an encoded video bitstream. The one or more processors are configured to parse or signal at least one syntax element for the block after all the luma coefficients of the block are parsed or signaled from or to the encoded video bitstream, wherein the at least one syntax element comprises at least one of a low-frequency non-separable transform index for the luma coefficients or a multiple transform selection index. The one or more processors are also configured to code the block in accordance with the at least one syntax element.

    HIGH-LEVEL CONSTRAINTS FOR TRANSFORM SKIP BLOCKS IN VIDEO CODING
    108.
    发明申请
    HIGH-LEVEL CONSTRAINTS FOR TRANSFORM SKIP BLOCKS IN VIDEO CODING 有权

    公开(公告)号：US20210314625A1

    公开(公告)日：2021-10-07

    申请号：US17220829

    申请日：2021-04-01

    Applicant: QUALCOMM Incorporated

    Inventor： Alican Nalci ,  Marta Karczewicz ,  Muhammed Zeyd Coban

    IPC: H04N19/70 ,  H04N19/124 ,  H04N19/46 ,  H04N19/176 ,  H04N19/174

    Abstract: An example device includes memory and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to receive a first slice header syntax element for a slice of the video data and determine a first value for the first slice header syntax element, the first value being indicative of whether dependent quantization is enabled. The one or more processors are configured to receive a second slice header syntax element for the slice of the video data and determine a second value for the second slice header syntax element, the second value being indicative of whether sign data hiding is enabled. The one or more processors are configured to determine whether transform skip residual coding is disabled for the slice based on the first value and the second value and decode the slice based on the determinations.

    Weighted prediction for video coding
    110.
    发明授权
    Weighted prediction for video coding 有权

    公开(公告)号：US11134246B2

    公开(公告)日：2021-09-28

    申请号：US16730708

    申请日：2019-12-30

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Han ,  Wei-Jung Chien ,  Chun-Chi Chen ,  Vadim Seregin ,  Marta Karczewicz

    IPC: H04N19/115 ,  H04N19/119 ,  H04N19/96 ,  H04N19/176

    Abstract: A device for processing video data includes a memory configured to store video data and one or more processors implemented in circuitry. The one or more processors are configured to generate a first weighting factor for a first reference picture in a first picture list using a second weighting factor for a second reference picture in a second picture list. The one or more processors are further configured to generate prediction information for a current block of video data using the first weighting factor and the second weighting factor.

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