公开(公告)号：US06835619B2

公开(公告)日：2004-12-28

申请号：US10215898

申请日：2002-08-08

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L21336

CPC classification number: H01L29/0847 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7885 ,  H01L29/792

Abstract: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.

公开(公告)号：US06777732B1

公开(公告)日：2004-08-17

申请号：US09503638

申请日：2000-02-14

Applicant: Kirk D. Prall ,  Robert Kerr ,  Christopher Murphy ,  D. Mark Durcan

Inventor： Kirk D. Prall ,  Robert Kerr ,  Christopher Murphy ,  D. Mark Durcan

IPC: H01L27108

CPC classification number: H01L27/10852 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10873 ,  H01L28/91

Abstract: A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.

公开(公告)号：US06632727B2

公开(公告)日：2003-10-14

申请号：US09939900

申请日：2001-08-27

Applicant: Howard E. Rhodes ,  Kirk D. Prall ,  Philip J. Ireland ,  Kenneth N. Hagen

Inventor： Howard E. Rhodes ,  Kirk D. Prall ,  Philip J. Ireland ,  Kenneth N. Hagen

IPC: H01L21425

CPC classification number: H01L21/26586 ,  H01L21/28518

Abstract: A method of forming electrical contacts includes the step of implanting ions into a contact hole at an angle to create an enlarged plug enhancement region at the bottom of a contact hole. Thus, even if the contact hole is misaligned, over-sized, or over-etched, the enlarged plug enhancement region contains subsequently formed barrier layers and other conductive materials to reduce current leakage into the underlying substrate or into adjacent circuit elements.

Abstract translation: 形成电触点的方法包括以一定角度将离子注入接触孔中以在接触孔的底部产生扩大的插塞增强区域的步骤。 因此，即使接触孔不对准，过大或过度蚀刻，扩大的插塞增强区域随后形成阻挡层和其他导电材料，以减少电流泄漏到下面的衬底或相邻的电路元件中。 >

公开(公告)号：US06501179B2

公开(公告)日：2002-12-31

申请号：US09921861

申请日：2001-08-02

Applicant: Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

Inventor： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC: H01L23485

CPC classification number: H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.

Abstract translation: 本发明包括在导电元件之间形成绝缘材料的方法。 在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。 另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。 在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。 在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

公开(公告)号：US06489665B2

公开(公告)日：2002-12-03

申请号：US09742706

申请日：2000-12-20

Applicant: Kirk D. Prall ,  Mike P. Violette

Inventor： Kirk D. Prall ,  Mike P. Violette

IPC: H01L27082

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L29/735

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

Abstract translation: 基本同心的横向双极晶体管及其形成方法。 基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。 栅极覆盖衬底和基极区域的至少一部分。 形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。 根据本发明的以下方法形成另外的双极晶体管。 在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。 发射极和集电极端子形成在基极区域的相对侧上。 在第一和第二离子注入期间，门用作掩模。 在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 另外，作为在制造集电极和发射极区域之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

公开(公告)号：US06406998B1

公开(公告)日：2002-06-18

申请号：US08596613

申请日：1996-02-05

Applicant: Kirk D. Prall ,  Gurtej S. Sandhu

Inventor： Kirk D. Prall ,  Gurtej S. Sandhu

IPC: H01L2144

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/28568

Abstract: Disclosed is a method using the implantation of ionized titanium for the formation of an electrical contact having a metal silicide diffusion barrier. The electrical contact is created by the steps of etching a contact opening over an active region on an in-process integrated circuit wafer, implanting metal ions into the contact opening, and annealing the contact opening to form a titanium silicide layer at the bottom of the contact opening adjacent to the underlying active region. In a further step, a titanium nitride layer is formed on the surface of the contact opening above the metal silicide layer, and the remainder of the contact opening is then filled by depositing tungsten into the contact opening. The method is especially useful for forming contacts having a high aspect ratio and for forming self-aligned contacts as it is capable of forming a uniform silicide layer at the bottom of a narrow contact opening.

Abstract translation: 公开了使用离子化钛的注入形成具有金属硅化物扩散阻挡层的电接触的方法。 通过以下步骤产生电接触：在过程中集成电路晶片上的有源区上蚀刻接触开口，将金属离子注入到接触开口中，以及退火接触开口以在底部形成硅化钛层 邻近底层有效区域的接触开口。 在另一步骤中，在金属硅化物层上方的接触开口的表面上形成氮化钛层，然后通过将钨沉积到接触开口中来填充接触开口的其余部分。 该方法对于形成具有高纵横比的接触和用于形成自对准接触是特别有用的，因为它能够在窄接触开口的底部形成均匀的硅化物层。

公开(公告)号：US06346455B1

公开(公告)日：2002-02-12

申请号：US09651946

申请日：2000-08-31

Applicant: Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

Inventor： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

IPC: H01L2120

CPC classification number: H01L28/87 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprising a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch resistant material, and etching the alternating layers thereby forming a capacitor structure having corrugated sides.

Abstract translation: 一种在半导体部件上形成波纹状电容器的方法。 形成波纹状电容器的方法包括在半导体组件上具有不同蚀刻速率的一系列沉积交替层的掺杂硅玻璃，用抗蚀刻材料覆盖交替层，并且蚀刻交替层，从而形成具有波纹状的电容器结构 。

公开(公告)号：US06274423B1

公开(公告)日：2001-08-14

申请号：US09236761

申请日：1999-01-25

Applicant: Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

Inventor： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

IPC: H01L218242

CPC classification number: H01L27/10852 ,  H01L27/10808

Abstract: An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.

Abstract translation: 用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。 该蚀刻工艺在形成于半导体衬底上的电容器结构中实施。电容器结构包括第一导体，第一导体上的电介质层和介电层上的第二导体。 第二导体具有横向邻近并远离第一导体延伸的水平区域。 蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。 或者，使用单个各向同性蚀刻去除第二导体的水平区域。

公开(公告)号：US06211007B1

公开(公告)日：2001-04-03

申请号：US08868058

申请日：1997-06-03

Applicant: Kirk D. Prall ,  Robert Kerr ,  Christopher Murphy ,  D. Mark Durcan

Inventor： Kirk D. Prall ,  Robert Kerr ,  Christopher Murphy ,  D. Mark Durcan

IPC: H01L218242

CPC classification number: H01L27/10852

Abstract: A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.

Abstract translation: 一种用于增强动态随机存取存储器中的刷新的过程，其中在形成存取晶体管部件之后，将n型杂质注入到电容器埋入接触中。 该工艺包括在衬底上形成栅极绝缘层，在栅极绝缘层上形成晶体管栅电极。 第一和第二晶体管源极/漏极区域形成在与栅电极的相对侧相邻的衬底上。 然后将N型杂质（优选磷原子）注入到用作电容器掩埋接触的第一源极/漏极区域中。

公开(公告)号：US6127236A

公开(公告)日：2000-10-03

申请号：US131454

申请日：1998-08-10

Applicant: Kirk D. Prall ,  Mike P. Violette

Inventor： Kirk D. Prall ,  Mike P. Violette

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/735

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L29/735

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

Abstract translation: 基本同心的横向双极晶体管及其形成方法。 基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。 栅极覆盖基板和基极区域的至少一部分。 形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。 根据本发明的以下方法形成另外的双极晶体管。 在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。 发射极和集电极端子形成在基极区域的相对侧上。 在第一和第二离子注入期间，门用作掩模。 在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 另外，作为在集电极和发射极区域制造之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。