公开(公告)号：US20220342821A1

公开(公告)日：2022-10-27

申请号：US17860263

申请日：2022-07-08

Applicant: Western Digital Technologies, Inc.

Inventor： Shay BENISTY

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F3/06 ,  G06F12/0868 ,  G06F12/0855 ,  G06F12/0871

Abstract: Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.

公开(公告)号：US20220342819A1

公开(公告)日：2022-10-27

申请号：US17241850

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Vincenzo Reina ,  Binbin Huo

IPC: G06F12/0804 ,  G01K3/06

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

公开(公告)号：US20220334968A1

公开(公告)日：2022-10-20

申请号：US17856947

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Mohamed ARAFA ,  Raj K. RAMANUJAN

IPC: G06F12/0804 ,  G06F12/12 ,  G06F12/02 ,  G06F12/0866

Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.

公开(公告)号：US11474940B2

公开(公告)日：2022-10-18

申请号：US16371082

申请日：2019-03-31

Applicant: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.

Inventor： David W. Cosby ,  Jonathan R. Hinkle ,  Jose M. Orro ,  Theodore B. Vojnovich

IPC: G06F12/0804 ,  G06F1/28

Abstract: Powering random access memory (RAM) modules with non-volatile memory components may include providing, by a power supply, a first output voltage to one or more RAM modules, each RAM module of the one or more RAM modules comprising a volatile memory component and a non-volatile memory component; providing, by the power supply, a second output voltage to one or more system components distinct from the one or more RAM modules; detecting a power event; sending, by the power supply, in response to detecting the power event, a signal to the one or more RAM modules to initiate a save operation, wherein the save operation comprises storing, for each of the one or more RAM modules, data from the volatile memory component to the non-volatile memory component; and ceasing, by the power supply, the second output voltage while maintaining the first output voltage to facilitate the save operation.

公开(公告)号：US20220318154A1

公开(公告)日：2022-10-06

申请号：US17704909

申请日：2022-03-25

Applicant: Oracle International Corporation

Inventor： Benjamin John Fuller

IPC: G06F12/0891 ,  G06F12/0804 ,  G06F12/0831 ,  G06F13/16

Abstract: Techniques described herein provide a handshake mechanism and protocol for notifying an operating system whether system hardware supports persistent cache flushing. System firmware may determine whether the hardware is capable of supporting a full flush of processor caches and volatile memory buffers in the event of a power outage or asynchronous reset. If the hardware is capable, then persistent cache flushing may be selectively enabled and advertised to the operating system. Once persistent cache flushing is enabled, the operating system and applications may treat data committed to volatile processor caches as persistent. If disabled or not supported by system hardware, then the platform may not advertise support for persistent cache flushing to the operating system.

公开(公告)号：US11461236B2

公开(公告)日：2022-10-04

申请号：US16882244

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/08 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

公开(公告)号：US11442898B2

公开(公告)日：2022-09-13

申请号：US16822406

申请日：2020-03-18

Applicant: Oracle International Corporation

Inventor： James Kremer ,  Mark Maybee ,  Natalie Ross ,  Pascal Ledru ,  Victor Latushkin ,  Ankit Gureja ,  Kimberly Morneau ,  Jingfei Zhang ,  Gavin Gibson

IPC: G06F16/20 ,  G06F16/172 ,  G06F3/06 ,  G06F11/14 ,  G06F16/182 ,  G06F16/185 ,  G06F12/0868 ,  G06F12/128 ,  H04L67/1095 ,  G06F11/10 ,  G06F12/0897 ,  G06F16/23 ,  G06F16/901 ,  G06F9/50 ,  G06F11/30 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/123 ,  H04L9/40 ,  G06F16/432 ,  G06F16/11 ,  G06F1/28 ,  G06F9/455 ,  G06F11/07 ,  G06F11/32 ,  G06F11/34 ,  G06F21/60 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  H04L67/1097 ,  G06F12/14 ,  H03M7/30 ,  H03M7/40

Abstract: Techniques described herein relate to systems and methods of data storage, and more particularly to providing layering of file system functionality on an object interface. In certain embodiments, file system functionality may be layered on cloud object interfaces to provide cloud-based storage while allowing for functionality expected from a legacy applications. For instance, POSIX interfaces and semantics may be layered on cloud-based storage, while providing access to data in a manner consistent with file-based access with data organization in name hierarchies. Various embodiments also may provide for memory mapping of data so that memory map changes are reflected in persistent storage while ensuring consistency between memory map changes and writes. For example, by transforming a ZFS file system disk-based storage into ZFS cloud-based storage, the ZFS file system gains the elastic nature of cloud storage.

公开(公告)号：US20220283941A1

公开(公告)日：2022-09-08

申请号：US17702505

申请日：2022-03-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US11437113B2

公开(公告)日：2022-09-06

申请号：US16876407

申请日：2020-05-18

Applicant: SK hynix Inc.

Inventor： Min Hwan Moon ,  Chung Un Na

IPC: G11C29/38 ,  G06F12/0804

Abstract: A memory system includes a storage medium including a target memory region having a plurality of memory units; and a controller configured to store data into one or more target memory units, each of which is estimated to take less time to perform a write operation thereon than any of the other memory units among the plurality of memory units, when performing a memory dump operation due to a sudden power off.

公开(公告)号：US20220276965A1

公开(公告)日：2022-09-01

申请号：US17744810

申请日：2022-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.