Choke circuit for a bus power supply

    公开(公告)号:US09800147B2

    公开(公告)日:2017-10-24

    申请号:US14274882

    申请日:2014-05-12

    摘要: The invention relates to a choke circuit and a bus power supply incorporating same. Such a coil choke circuit includes an inductor connected between a first input terminal and a first output terminal, a boost circuit connected between a second input terminal and a second output terminal for increasing the voltage level that is output by the second output terminal. A switching element is connected in parallel to the boost circuit for bypassing the boost circuit. Additionally, a comparator is connected between the first input terminal and the first output terminal for detecting a potential difference across the inductor; wherein in case the comparator detects a potential difference higher than a threshold, the switching element is controlled to be in an OFF state; and in case the comparator detects a potential difference lower than or equal to the threshold, the switching element is controlled to be in an ON state.

    Control system using power line communication

    公开(公告)号:US09798337B2

    公开(公告)日:2017-10-24

    申请号:US14660409

    申请日:2015-03-17

    发明人: Yu-Cheng Hung

    CPC分类号: G05F1/12 H04B3/56

    摘要: A control system includes a control device adapted to be connected to a live line and a neutral line that transmit a grid power, and to a load via a first power line and a second power line. The control device includes: a first switch adapted to be connected between the live line and the first power line; a second switch adapted to be connected between the neutral line and the second power line; a coupler adapted to be connected to the first power line, receiving a communication signal, and coupling the communication signal to the first power line; and a controller controlling the first and second switches to synchronously alternate between an ON state and an OFF state, and outputting the communication signal to the coupler when the first and second switches operate in the OFF state.

    PARALLEL TESTING OF A CONTROLLER AREA NETWORK BUS CABLE

    公开(公告)号:US20170288730A1

    公开(公告)日:2017-10-05

    申请号:US15629613

    申请日:2017-06-21

    IPC分类号: H04B3/56 H04B17/00 H04B3/46

    CPC分类号: H04B3/56 H04B3/46 H04B17/00

    摘要: A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processing system to cause the processing system to perform a method that includes sending a data testing signal through a data lead of a cable via a first interface, sending a power signal through a power lead of the cable via the first interface, receiving and analyzing the data testing signal from the data lead of the cable via a second interface, and receiving and analyzing the power signal passing through the power lead of the cable via the second interface.

    SYSTEM FOR TRANSMITTING CONTROL SIGNALS OVER TWISTED PAIR CABLING USING COMMON MODE OF TRANSFORMER

    公开(公告)号:US20170230204A1

    公开(公告)日:2017-08-10

    申请号:US15016710

    申请日:2016-02-05

    申请人: ADVOLI Limited

    IPC分类号: H04L25/02 H04B3/56

    摘要: A system for transmitting control systems over twisted pair cabling. The system includes a first microcontroller transmitting a first single ended signal and receiving a second single ended signal. It also includes a first differential transmitter coupled to the first microcontroller for receiving the first single ended signal from the first microcontroller and converting it to a differential signal over a first differential line and a second differential line; and, a first differential receiver coupled to the first microcontroller for receiving a third differential line and a fourth differential line and converting it to a differential receiver signal, the differential receiver signal coupled to the second single ended signal. The system has a first transformer having first, second, third, and fourth center-tapped coils, the first differential line coupled to the center tap of the first coil, the second differential line coupled to the center tap of the fourth coil, the third differential line coupled to the center tap of the second coil, and the fourth differential line coupled to the center tap of the third coil, whereby the common mode of the first transformer is used to transmit a first control signal and to receive control signal responses over the twisted pair at the first processor.