公开(公告)号：US5313088A

公开(公告)日：1994-05-17

申请号：US762208

申请日：1991-09-19

Applicant: Nobumitsu Takahashi ,  Mitsuasa Takahashi

Inventor： Nobumitsu Takahashi ,  Mitsuasa Takahashi

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/34

CPC classification number: H01L29/7811 ,  H01L27/0255 ,  H01L29/7805 ,  H01L2224/05624 ,  H01L2224/85424 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/1305 ,  H01L2924/13091

Abstract: A vertical field effect transistor of the structure having a gate pad and a gate finger, includes a semiconductor substrate of a first conduction type, and a first diffusion region of a second conduction type opposite to the first conduction type, formed in a principal surface of the substrate under the gate pad and the gate finger. A second diffusion region of the second conduction type is formed in the principal surface of the substrate and electrically connected to a source electrode so as to form a protection diode between the substrate and the second diffusion region. The second diffusion region is separated from the first diffusion region.

Abstract translation: 具有栅极焊盘和栅极指状的结构的垂直场效应晶体管包括：第一导电类型的半导体衬底和与第一导电类型相反的第二导电类型的第一扩散区域， 栅极衬底和栅极指。 第二导电类型的第二扩散区形成在基板的主表面上并与源电极电连接，从而在基板和第二扩散区之间形成保护二极管。 第二扩散区域与第一扩散区域分离。

公开(公告)号：US5285102A

公开(公告)日：1994-02-08

申请号：US988386

申请日：1992-12-08

Applicant: Peter S. Ying

Inventor： Peter S. Ying

IPC: H01L21/3105 ,  H01L21/762 ,  H01L23/532 ,  H01L29/34 ,  H01L29/04

CPC classification number: H01L21/31051 ,  H01L21/76229 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S148/133

Abstract: A method for forming a planar insulating layer over the surface of a semiconductor workpiece 8 which includes at least one low region 13 is discussed herein. The first step is to form a layer of blocking material 14 on the surface of the workpiece 8. A first material region 20 is then formed in the low region 13 and an insulating layer 21 is formed over the surface of the workpiece 8 including the first material region 20. The workpiece 8 is then heated in the presence of an active ambient such that the insulation layer 21 reflows and also so that the first material 20 region reacts with the active ambient to create an internal stress in said insulation layer 21. Other systems and methods are also disclosed.

Abstract translation: 这里讨论了在包括至少一个低区域13的半导体工件8的表面上形成平面绝缘层的方法。 第一步是在工件8的表面上形成一层阻挡材料14.然后在低区域13中形成第一材料区域20，并且在工件8的表面上形成绝缘层21，包括第一 然后在活性环境的存在下加热工件8，使得绝缘层21回流并且还使得第一材料20区域与活性环境反应以在所述绝缘层21中产生内部应力。其它 还公开了系统和方法。

公开(公告)号：US5049953A

公开(公告)日：1991-09-17

申请号：US465750

申请日：1990-01-18

Applicant: Teruyoshi Mihara ,  Kenji Yao ,  Tsutomu Matsushita ,  Yoshinori Murakami

Inventor： Teruyoshi Mihara ,  Kenji Yao ,  Tsutomu Matsushita ,  Yoshinori Murakami

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/48 ,  H01L27/02 ,  H01L29/10 ,  H01L29/34

CPC classification number: H01L29/7839 ,  Y10S257/902

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, in which a drain region is formed in the substrate, and a gate electrode is formed on the surface of the substrate via an insulating film formed thereon. A Schottky metal as a source region is formed in the surface of the substrate away from the drain region, the Schottky metal and the substrate constituting a Schottky junction at an interface therebetween near the gate electrode. A shield layer of a second conductivity type is interposed between the Schottky metal and the substrate except in the Schottky junction. The gate electrode controls tunnel current at the Schottky junction.

Abstract translation: 半导体器件包括：第一导电类型的半导体衬底，其中在衬底中形成漏极区，并且通过形成在其上的绝缘膜在衬底的表面上形成栅电极。 作为源极区域的肖特金属金属在远离漏极区域的肖特基金属和衬底的与栅极电极附近的界面处构成肖特基结的表面上形成。 第二导电类型的屏蔽层介于除了肖特基结之外的肖特基金属和基板之间。 栅电极控制肖特基结的隧道电流。

公开(公告)号：US4912540A

公开(公告)日：1990-03-27

申请号：US230696

申请日：1988-08-05

Applicant: Craig S. Sander ,  Richard K. Klein ,  Tat C. Choi

Inventor： Craig S. Sander ,  Richard K. Klein ,  Tat C. Choi

IPC: H01L21/768 ,  H01L29/04 ,  H01L23/48 ,  H01L29/34

CPC classification number: H01L21/76895 ,  H01L21/7684 ,  H01L21/76877

Abstract: A reduced area butting contact structure (10') is provided, which is especially suited for four-transistor static RAM cells. A structure is formed which includes a doped silicon region and one or more layers of polysilicon and oxide situated thereabove, one of which layers of polysilicon may be a gate polysilicon. An anisotropic etch is then performed through all upper layers including any upper polysilicon layers which may be present, but stopping at the doped silicon region and any gate polysilicon layers present, to form a contact hole (26'). The contact hole is filled with a conductive plug (32) of a material such as tungsten or polysilicon and etched back. In either case, contact with all polysilicon layers present and the doped silicon region is made. In the anisotropic etching process, a two-step etch is employed. The first etch is non-specific as to material, etching all relevant materials (polysilicon and oxide) at substantially the same rate and is continued through any upper polysilicon layers, but is terminated prior to etching the doped silicon region or any gate polysilicon layers (22). The second etch is specific as to material, etching silicon dioxide faster than polysilicon or silicon, and thus stops at the gate polysilicon layer and the doped silicon region.

Abstract translation: 提供了减小面积对接接触结构（10'），其特别适用于四晶体管静态RAM单元。 形成了包括掺杂硅区域和位于其上方的一层或多层多晶硅和氧化物的结构，其中一层多晶硅可以是栅极多晶硅。 然后通过所有上层进行各向异性蚀刻，所述上层包括可能存在的任何上多晶硅层，但在掺杂硅区域和存在的任何栅多晶硅层停止以形成接触孔（26'）。 接触孔填充有诸如钨或多晶硅的材料的导电插塞（32）并被回蚀。 在任一种情况下，与存在的所有多晶硅层和掺杂的硅区域接触。 在各向异性蚀刻工艺中，采用两步蚀刻。 第一蚀刻对于材料是非特异性的，以基本上相同的速率蚀刻所有相关材料（多晶硅和氧化物）并且继续通过任何上多晶硅层，但是在蚀刻掺杂硅区域或任何栅极多晶硅层之前终止 22）。 第二蚀刻对于材料是特定的，比多晶硅或硅更快地蚀刻二氧化硅，因此停止在栅极多晶硅层和掺杂的硅区域。

公开(公告)号：US4827325A

公开(公告)日：1989-05-02

申请号：US46523

申请日：1987-05-04

Applicant: Zvi Or-Bach ,  Joseph Salzman

Inventor： Zvi Or-Bach ,  Joseph Salzman

IPC: H01L23/31 ,  H01L23/525 ,  H01L27/092 ,  H01L27/02 ,  H01L29/34

CPC classification number: H01L23/3157 ,  H01L23/5258 ,  H01L27/0927 ,  H01L2924/0002

Abstract: A multilayer optical coating for semiconductor substrates characterized in that it is etchable by conventional techniques used for fabrication of integrated circuits and has high reflectivity.

Abstract translation: 一种用于半导体衬底的多层光学涂层，其特征在于可通过用于制造集成电路的常规技术进行蚀刻，并具有高反射率。

公开(公告)号：US4801994A

公开(公告)日：1989-01-31

申请号：US21937

申请日：1987-03-05

Applicant: Gerardus G. P. Van Gorkom ,  Arthur M. E. Hoeberechts

Inventor： Gerardus G. P. Van Gorkom ,  Arthur M. E. Hoeberechts

IPC: H01J1/30 ,  H01J1/308 ,  H01J29/04 ,  H01J31/12 ,  H01J31/38 ,  H01J37/073 ,  H01L21/027 ,  H01L33/00 ,  H01L29/12 ,  H01L29/34

CPC classification number: H01J1/308

Abstract: By providing an intrinsic semiconductor region in a reverse biased junction cathode between an n-type surface region and a p-type zone, a maximum field is present over the intrinsic region in the operating condition. The efficiency of the cathode is increased because avalanche multiplication can now occur over a greater distance, while in addition electrons to be emitted at a sufficient energy are generated by means of tunneling.

公开(公告)号：US4796075A

公开(公告)日：1989-01-03

申请号：US852473

申请日：1986-04-15

Applicant: Ralph G. Whitten

Inventor： Ralph G. Whitten

IPC: H01L23/525 ,  H01L27/02 ,  H01L23/48 ,  H01L29/34

CPC classification number: H01L23/5256 ,  H01L2924/0002

Abstract: A fusible link structure and method of making the same for use in integrated circuit structures is provided in which the fusible link comprises, in one embodiment, an alloy of platinum and silicon. The preferred alloy comprises the eutectic mixture having approximately 23 atomic percent silicon. Electrical connections to the fusible link are preferably provided by a layer of aluminum on a layer of material, preferably an alloy of titanium and tungsten wherein the titanium and tungsten alloy is disposed between the fusible link and the aluminum layer, and serves as a diffusion barrier for preventing diffusion of the aluminum into the fusible link. In a preferred embodiment, a fusible link is deposited on a relatively thick dielectric layer, preferably more than 10,000 .ANG. thick, having a relatively low thermal conductivity. The preferred method of depositing the fusible link is sputtering from a target comprising the platinum-silicide alloy, thus achieving a fuse element having uniform composition throughout its cross section. A fuse of this type has high reliability, requires low fusing current, and is dielectrically encapsulated sealed within the integrated circuit structure.

Abstract translation: 提供了一种用于集成电路结构的可熔链接结构及其制造方法，其中在一个实施例中，可熔连接件包括铂和硅的合金。 优选的合金包括具有约23原子％硅的共晶混合物。 与可熔连接件的电连接优选地通过一层铝材料提供，优选钛和钨的合金，其中钛和钨合金设置在可熔连接件和铝层之间，并且用作扩散阻挡层 用于防止铝扩散到熔丝中。 在优选实施例中，可熔连接层沉积在相对较厚的电介质层上，优选厚度大于10,000，具有较低的热导率。 沉积可熔连接件的优选方法是从包括铂硅化物合金的靶溅射，从而实现了在其横截面上具有均匀组成的熔丝元件。 这种类型的保险丝具有高可靠性，需要低熔断电流，并且被集成地封装在集成电路结构内。

公开(公告)号：US4761678A

公开(公告)日：1988-08-02

申请号：US19281

申请日：1987-02-26

Applicant: Hideto Goto

Inventor： Hideto Goto

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34

CPC classification number: H01L21/76897 ,  H01L23/5329 ,  H01L28/40 ,  H01L2924/0002

Abstract: An integrated circuit semiconductor device in which a first insulating layer including a silicon nitride film and a second insulating layer including a silicon oxide film thermally grown are formed on a major surface of a silicon substrate and contacted each other at respective side edges to form a boundary is disclosed. First and second electrodes are formed on the first and second insulating layers, respectively and separated each other with a gap. A third insulating layer fills the gap and contacts to both of peripheral surface sections of the first and second insulating layers extending from the boundary, respectively.

Abstract translation: 一种集成电路半导体器件，其中在硅衬底的主表面上形成包括氮化硅膜的第一绝缘层和包含热生长的氧化硅膜的第二绝缘层，并在相应的侧边缘彼此接触以形成边界 被披露。 第一和第二电极分别形成在第一绝缘层和第二绝缘层上，并且间隔开。 第三绝缘层填充间隙并分别接触从边界延伸的第一和第二绝缘层的外周表面部分。

公开(公告)号：US4750028A

公开(公告)日：1988-06-07

申请号：US105465

申请日：1987-10-02

Applicant: Adrianus W. Ludikhuize

Inventor： Adrianus W. Ludikhuize

IPC: H01L29/06 ,  H01L29/34

CPC classification number: H01L29/0619

Abstract: A semiconductor device has a surface zone which forms a planar pn junction with the surrounding substrate, this pn junction being biased in operation in the reverse direction. In order to increase the breakdown voltage, one or more floating zones are located beside the pn junction within the range of the depletion zone, which also form planar pn junctions with the substrate. According to the invention, the floating zones have an overall doping of at least 3.multidot.10.sup.11 and at most 5.multidot.10.sup.12 atoms/cm.sup.2, as a result of which they are substantially depleted at a high reverse voltage.

Abstract translation: 半导体器件具有与周围衬底形成平面pn结的表面区，该pn结在反向工作时被偏置。 为了提高击穿电压，在耗尽区的范围内，在pn结旁边有一个或多个浮动区，其也与衬底形成平面的pn结。 根据本发明，浮动区域具有至少3×10 11和至多5×10 12原子/ cm 2的总掺杂，其结果是它们在高反向电压下基本上耗尽。

公开(公告)号：US4742384A

公开(公告)日：1988-05-03

申请号：US476722

申请日：1983-03-18

Applicant: Jacques I. Pankove ,  Ming L. Tarng

Inventor： Jacques I. Pankove ,  Ming L. Tarng

IPC: H01L21/314 ,  H01L23/29 ,  H01L29/34

CPC classification number: H01L21/314 ,  H01L23/298 ,  H01L2924/0002

Abstract: A technique for passivating a PN junction adjacent a surface of a semiconductor substrate comprises coating the area of the surface adjacent the PN junction with a layer of hydrogenated amorphous silicon containing between about 5 and about 50 atomic percent of hydrogen.

Abstract translation: 用于钝化邻近半导体衬底的表面的PN结的技术包括用含有约5至约50原子百分比的氢的氢化非晶硅层涂覆邻近PN结的表面的区域。