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    Dynamic threshold voltage MOSFET on SOI
    91.
    发明授权
    Dynamic threshold voltage MOSFET on SOI 有权
    SOI上的动态阈值电压MOSFET

    公开(公告)号：US07045873B2

    公开(公告)日：2006-05-16

    申请号：US10728750

    申请日：2003-12-08

    申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

    发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

    IPC分类号： H01L29/00

    CPC分类号： H01L29/783

    摘要： Provision of a body control contact adjacent a transistor and between the transistor and a contact to the substrate or well in which the transistor is formed allows connection and disconnection of the substrate of the transistor to and from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold which maintains good performance at low supply voltages and reduces power consumption/dissipation which is particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate in disconnected from a voltage source in the “on” state) are avoided since the substrate is discharged when the transistor is switched to the “off” state. The transistor configuration can be employed with both n-type and p-type transistors which may be in complementary pairs.

    摘要翻译： 提供与晶体管相邻并且晶体管与形成晶体管的衬底或阱的接触之间的身体控制接触允许晶体管的衬底与零（接地）或基本上任意的低电压的连接和断开 根据施加到晶体管的栅极的控制信号，使晶体管呈现可变阈值，其在低电源电压下保持良好的性能，并降低了在便携式电子设备中特别有利的功耗/耗散。 避免浮体效应（当晶体管基板与电压源处于“导通”状态断开时），因为当晶体管切换到“关闭”状态时，衬底被放电。 晶体管配置可以与可以互补对的n型和p型晶体管一起使用。

    Semiconductor integrated circuit device
    93.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20050146961A1

    公开(公告)日：2005-07-07

    申请号：US11042172

    申请日：2005-01-26

    申请人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC分类号： H01L27/10 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/02

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    摘要翻译： 现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致 不对称性导致了微图案化困难的问题的发生。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分为两部分，它们设置在N型阱区NW 1的相对侧，并形成为 形成晶体管的扩散层没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

    Flat panel display
    94.
    发明申请
    Flat panel display 有权
    平板显示器

    公开(公告)号：US20050077844A1

    公开(公告)日：2005-04-14

    申请号：US10938000

    申请日：2004-09-10

    申请人： Jae-Bon Koo ,  Byoung-Deog Choi

    发明人： Jae-Bon Koo ,  Byoung-Deog Choi

    IPC分类号： H01L51/50 ,  H01L27/12 ,  H01L27/32 ,  H01L29/78 ,  H01L29/786 ,  H05B33/00 ,  H01L29/792

    CPC分类号： H01L29/78615 ,  H01L27/12 ,  H01L27/3262 ,  H01L29/783 ,  H01L29/78639

    摘要： A high-speed flat panel display having a long lifetime. Thin film transistors in a pixel portion having a plurality of pixels are contacted differently from thin film transistors in driving circuit portions for driving the pixels, thereby enhancing luminance uniformity and reducing power consumption. The thin film transistors each have a channel region and a body contact region for applying a predetermined voltage to the channel region. At least one thin film transistor in the pixel portion is a source-body contact thin film transistor having the body contact region connected to one of source and drain electrodes so that the predetermined voltage can be provided to the channel region. Each thin film transistor in the driving circuit portion is a gate-body contact thin film transistor having the body contact region connected to the gate electrode so that a predetermined voltage can be provided to the channel region.

    摘要翻译： 一种寿命长的高速平板显示器。 具有多个像素的像素部分中的薄膜晶体管与用于驱动像素的驱动电路部分中的薄膜晶体管不同地接触，从而增强亮度均匀性并降低功耗。 薄膜晶体管各自具有用于向沟道区施加预定电压的沟道区和体接触区。 像素部分中的至少一个薄膜晶体管是源体接触薄膜晶体管，其具有连接到源极和漏极之一的主体接触区域，从而可以将预定电压提供给沟道区域。 驱动电路部分中的每个薄膜晶体管是具有连接到栅电极的体接触区域的门体接触薄膜晶体管，从而可以向沟道区域提供预定电压。

    Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication
    95.
    发明申请
    Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication 失效
    基于鳍的双重多晶硅动态阈值CMOS FET与间隔栅极和制造方法

    公开(公告)号：US20040207019A1

    公开(公告)日：2004-10-21

    申请号：US10843029

    申请日：2004-05-11

    发明人： Andres Bryant ,  K. Paul Muller ,  Edward J. Nowak

    IPC分类号： H01L027/148

    CPC分类号： H01L29/785 ,  H01L21/2815 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/783

    摘要： The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-source/drain capacitance. The low body-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.

    摘要翻译： 本发明提供一种动态阈值（DT）CMOS FET及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供一种DT CMOS FET，其在栅极和主体之间具有短的低电阻连接，并且具有低的体源/漏极电容。 低体积/漏极电容使用薄的翅片型体实现。 栅极和体接触之间的低电阻连接是通过使栅极和主体接触在翅片的相对的长边上对准来实现的，桥与电极连接门和主体的窄鳍的顶部之间形成桥。

    SRAM cells with two P-well structure
    97.
    发明授权
    SRAM cells with two P-well structure 有权
    具有两个P阱结构的SRAM单元

    公开(公告)号：US06677649B2

    公开(公告)日：2004-01-13

    申请号：US09565535

    申请日：2000-05-05

    申请人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC分类号： H01L2976

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    摘要翻译： 现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致 不对称性导致了微图案化困难的问题的发生。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

    SOI CMOS device with body to gate connection
    98.
    发明授权
    SOI CMOS device with body to gate connection 有权

    公开(公告)号：US06670655B2

    公开(公告)日：2003-12-30

    申请号：US09837839

    申请日：2001-04-18

    申请人： Eric John Lukes ,  Patrick Lee Rosno ,  James David Strom

    发明人： Eric John Lukes ,  Patrick Lee Rosno ,  James David Strom

    IPC分类号： H01L27148

    CPC分类号： H01L27/1203 ,  H01L29/783

    摘要： A method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.

    Semiconductor device and its fabrication method
    99.
    发明申请
    Semiconductor device and its fabrication method 失效
    半导体器件及其制造方法

    公开(公告)号：US20030008452A1

    公开(公告)日：2003-01-09

    申请号：US10188108

    申请日：2002-07-03

    申请人： Matsushita Electric Industrial Co., LTd.

    发明人： Takeshi Takagi

    IPC分类号： H01L021/8238

    CPC分类号： H01L29/66651 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78639

    摘要： A semiconductor device comprises an Si substrate, an isolation insulating film formed on the Si substrate, an Si layer formed on the Si substrate, a gate oxide film formed on the Si layer, a gate electrode formed on the gate oxide film, a sidewall formed on the side face of the gate electrode, a gate silicide film formed on the gate electrode, source and drain regions formed at both the sides of the gate electrode and including a part of the Si layer, and a silicide film formed on the source and drain regions. Because the source and drain regions are formed on a layer-insulating film so as to be overlayed, it is possible to decrease the active region and cell area of a device. Thereby, a high-speed operation and high integration can be realized.

    摘要翻译： 半导体器件包括Si衬底，形成在Si衬底上的隔离绝缘膜，形成在Si衬底上的Si层，形成在Si层上的栅极氧化膜，形成在栅氧化膜上的栅电极，形成侧壁 在栅电极的侧面上，形成在栅电极上的栅极硅化物膜，形成在栅电极的两侧的源极和漏极区，并且包括一部分Si层，以及形成在源极上的硅化物膜 漏区。 因为源极和漏极区域形成在层间绝缘膜上以便被覆盖，所以可以减小器件的有源区域和单元面积。 由此，能够实现高速运转，高集成化。

    Semiconductor device and method of manufacture thereof
    100.
    发明授权
    Semiconductor device and method of manufacture thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US06426532B1

    公开(公告)日：2002-07-30

    申请号：US09720714

    申请日：2001-04-19

    申请人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

    发明人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

    IPC分类号： H01L31119

    CPC分类号： H01L29/783 ,  H01L21/84 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78654

    摘要： A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.

    摘要翻译： 根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅电极的侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖对应的器件隔离区的一部分的第二导电类型半导体层，作为源区和/或漏区的第二导电类型半导体层。 栅电极和第一导电类型半导体层彼此电连接。 第二导电类型半导体层设置在第一导电类型半导体层之上，并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。