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    Mixed-precision floating point operations from a single instruction opcode
    91.
    发明授权
    Mixed-precision floating point operations from a single instruction opcode 失效
    来自单指令操作码的混合精度浮点运算

    公开(公告)号：US4823260A

    公开(公告)日：1989-04-18

    申请号：US119547

    申请日：1987-11-12

    申请人： Michael T. Imel ,  Konrad Lai ,  Glenford J. Myers ,  Randy Steck ,  James Valerio

    发明人： Michael T. Imel ,  Konrad Lai ,  Glenford J. Myers ,  Randy Steck ,  James Valerio

    IPC分类号： G06F7/57 ,  G06F7/48

    CPC分类号： G06F7/483 ,  G06F2207/3816 ,  G06F7/49957

    摘要： Apparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode.

    摘要翻译： 用于从单个指令操作码在微处理器的浮点单元中执行混合精度计算的装置。 可以将80位浮点寄存器（44）指定为浮点指令的源地址或目标地址。 当目的地的地址范围指示（26）指定浮点寄存器时，该操作的结果不会舍入到指令指定的精度，而是舍入（58）到扩展的80位精度并加载到 浮点寄存器（FP-44）。 当源地址范围指示（26）FP寄存器被寻址时，无论指令指定的精度如何，数据都以扩展精度从FP寄存器加载。 以这种方式，可以使用实际和长期实际的操作来使用扩展精度数字，而无需在操作码中明确指定。

    METHOD AND SYSTEM FOR TRAINING MACHINE LEARNING MODELS USING DYNAMIC FIXED-POINT DATA REPRESENTATIONS
    92.
    发明公开
    METHOD AND SYSTEM FOR TRAINING MACHINE LEARNING MODELS USING DYNAMIC FIXED-POINT DATA REPRESENTATIONS 审中-公开

    公开(公告)号：US20230376769A1

    公开(公告)日：2023-11-23

    申请号：US17747579

    申请日：2022-05-18

    申请人： Seyed Alireza GHAFFARI ,  Eyyüb HACHMIE SARI ,  Vahid PARTOVI NIA

    发明人： Seyed Alireza GHAFFARI ,  Eyyüb HACHMIE SARI ,  Vahid PARTOVI NIA

    IPC分类号： G06N3/08 ,  G06F7/499

    CPC分类号： G06N3/084 ,  G06F7/49957

    摘要： Systems and methods for training a machine learning model. The methods comprise receiving a plurality of first data points, each data point of the first data points being represented in a floating-point representation. The methods further comprise converting the plurality of first data points into a corresponding plurality of second data points. Each of the second data points is represented in a dynamic fixed-point representation. The plurality of second data points may include: for each second data point, the sign component of the corresponding first data point, for each second data point, a dynamic fixed-point mantissa component, and one or more shared fraction components. At least two of the second data points share a value of a shared fraction component of the one or more shared fraction components. The methods further comprise performing integer computations during training of the machine learning model using the second data points.

    Fused floating point datapath with correct rounding
    98.
    发明授权
    Fused floating point datapath with correct rounding 有权
    熔点浮点数据路径正确舍入

    公开(公告)号：US09552190B1

    公开(公告)日：2017-01-24

    申请号：US15133363

    申请日：2016-04-20

    申请人： Altera Corporation

    发明人： Martin Langhammer ,  Bogdan Pasca

    IPC分类号： G06F7/00 ,  G06F7/499 ,  G06F7/483

    CPC分类号： G06F7/49915 ,  G06F7/48 ,  G06F7/483 ,  G06F7/49957

    摘要： In accordance with some embodiments, a floating point number datapath circuitry, e.g., within an integrated circuit programmable logic device is provided. The datapath circuitry may be used for computing a rounded absolute value of a mantissa of a floating point number. The floating point datapath circuitry may have only a single adder stage for computing a rounded absolute value of a mantissa of the floating point number based on one or more bits of an unrounded mantissa of the floating point number. The unrounded and rounded mantissas may include a sign bit, a sticky bit, a round bit, and/or a least significant bit, and/or other bits. The unrounded mantissa may be in a format that includes negative numbers (e.g., 2's complement) and the rounded mantissa may be in a format that may include a portion of the floating point number represented as a positive number, (e.g., signed magnitude).

    摘要翻译： 根据一些实施例，提供浮点数数据路径电路，例如在集成电路可编程逻辑器件内。 数据路径电路可用于计算浮点数的尾数的舍入绝对值。 浮点数据路径电路可以仅具有单个加法器级，用于基于浮点数的未被四舍五入的尾数的一个或多个位来计算浮点数的尾数的舍入绝对值。 未被四舍五入的尾数可以包括符号位，粘性位，圆比特和/或最低有效位和/或其他位。 未包围的尾数可以是包括负数（例如，2的补码）的格式，并且舍入的尾数可以是可以包括表示为正数的浮点数的一部分（例如，有符号的大小）的格式。

    CALCULATION CONTROL INDICATOR CACHE
    99.
    发明申请
    CALCULATION CONTROL INDICATOR CACHE 有权
    计算控制指示器缓存

    公开(公告)号：US20160004509A1

    公开(公告)日：2016-01-07

    申请号：US14748956

    申请日：2015-06-24

    申请人： VIA ALLIANCE SEMICONDUCTOR CO, LTD.

    发明人： THOMAS ELMER

    IPC分类号： G06F7/487 ,  G06F7/485 ,  G06F17/16

    CPC分类号： G06F7/483 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/49957 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/38 ,  G06F9/3893 ,  G06F17/16

    摘要： An arithmetic operation is performed using a first instruction execution unit to generate an intermediate result vector and a plurality of calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The intermediate result vector and the plurality of calculation control indicators are stored in memory external to the instruction execution unit, and later read by a second instruction execution unit to complete the arithmetic operation.

    摘要翻译： 使用第一指令执行单元执行算术运算，以产生中间结果向量和指示如何继续从中间结果向量生成最终结果的后续计算的多个计算控制指示符。 中间结果矢量和多个计算控制指示器存储在指令执行单元外部的存储器中，并且稍后由第二指令执行单元读取以完成算术运算。

    STANDARD FORMAT INTERMEDIATE RESULT
    100.
    发明申请
    STANDARD FORMAT INTERMEDIATE RESULT 有权
    标准格式中间结果

    公开(公告)号：US20160004506A1

    公开(公告)日：2016-01-07

    申请号：US14749002

    申请日：2015-06-24

    申请人： VIA ALLIANCE SEMICONDUCTOR CO, LTD.

    发明人： THOMAS ELMER

    IPC分类号： G06F7/483 ,  G06F9/30 ,  G06F9/38 ,  G06F7/544

    CPC分类号： G06F7/483 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/49957 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/38 ,  G06F9/3893 ,  G06F17/16

    摘要： A microprocessor comprises an instruction pipeline, a shared memory, and first and second arithmetic processing units in the instruction pipeline, each capable of reading or receiving operands from and writing or providing results to the shared memory. The first arithmetic processing unit performs a first portion of a mathematical operation to produce an intermediate result vector that is not a complete, final result of the mathematical operation. The first arithmetic processing unit generates a plurality of non-architectural calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The second arithmetic processing unit performs a second portion of the mathematical operation, in accordance with the calculation control indicators, to produce a complete, final result of the mathematical operation.

    摘要翻译： 微处理器包括指令流水线，共享存储器以及指令流水线中的第一和第二算术处理单元，每个能够读取或接收来自共享存储器的操作数和向其写入或提供结果。 第一算术处理单元执行数学运算的第一部分以产生不是数学运算的完整最终结果的中间结果矢量。 第一算术处理单元生成多个非架构计算控制指示符，其指示如何继续从中间结果向量生成最终结果的后续计算。 第二算术处理单元根据计算控制指示符执行​​数学运算的第二部分，以产生数学运算的完整的最终结果。