公开(公告)号：US09978625B2

公开(公告)日：2018-05-22

申请号：US15170459

申请日：2016-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yung-Yao Lee ,  Jui-Chun Peng ,  Ho-Ping Chen ,  Heng-Hsin Liu

IPC: H01L21/308 ,  H01L21/68 ,  H01L21/3065 ,  G03F1/42

CPC classification number: H01L21/682 ,  G03F1/42 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/681 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A semiconductor method is disclosed. The semiconductor method is performed upon semiconductor wafers, wherein each of the semiconductor wafers includes a first exposure field and a second exposure field, and each of the first exposure field and the second exposure field includes a first alignment mark and a second alignment mark. The method includes: determining a first alignment pattern for a first wafer by selecting one of the alignment marks of the first exposure field, and selecting one of the alignment marks of the second exposure field; performing the aligning operation upon the first semiconductor wafer by using the first alignment pattern; determining a second alignment pattern for a second wafer by selecting one of the alignment marks of the first exposure field, and selecting one of the alignment marks of the second exposure field, wherein the first alignment pattern is different from the second alignment pattern.

公开(公告)号：US20180107073A1

公开(公告)日：2018-04-19

申请号：US15534055

申请日：2016-05-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

Inventor： Guojing MA ,  Changjian XU ,  Dan WANG

IPC: G02F1/1337 ,  G02F1/13 ,  G01B11/14 ,  G03F1/42 ,  H05K3/00

CPC classification number: G02F1/133753 ,  G01B11/14 ,  G02F1/1303 ,  G02F1/133788 ,  G03F1/42 ,  H05K3/0002

Abstract: A mask including a plurality of baffles, a frame and a light transmission region, and a photo alignment method are provided. A support component and a movable component are disposed on the frame. The baffle is configured to block the light transmission region. The support component is configured to support the baffle which blocks the light transmission region. The movable component is configured to move the baffle to a position blocking the light transmission region.

公开(公告)号：US20180053673A1

公开(公告)日：2018-02-22

申请号：US15367692

申请日：2016-12-02

Applicant: MIDAS SYSTEM CO., LTD.

Inventor： Gon Chul LEE ,  Heung Ki MIN ,  Jun Hyeong LEE ,  Jae Geun JEON

IPC: H01L21/68 ,  G03F1/42

CPC classification number: H01L21/682 ,  G03F1/42 ,  G03F7/70691 ,  G03F7/70716 ,  G03F7/70808 ,  G03F7/70833 ,  G03F9/7034

Abstract: Embodiments of the invention relate to a stage leveling device for a high-performance mask aligner, having enhanced leveling maintenance and, in particular, a novel technology of preventing leveling misalignment by firmly fixing a leveling-completed wafer stage. The stage leveling device, according to an embodiment of the invention addresses the problems experienced by conventional leveling devices. According to at least one embodiment, when a locking ring inserted at an outer side of a leveling rod maintains an inclined state, locking is performed such that an inner circumferential surface of the locking ring fixes opposite sides of the leveling rod by applying pressure thereto and, when the locking ring maintains a horizontal state, unlocking is performed such that the inner circumferential surface of the locking ring is spaced apart from the leveling rod.

公开(公告)号：US09846359B1

公开(公告)日：2017-12-19

申请号：US15392297

申请日：2016-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hwa Oh ,  Seung Yoon Lee ,  Jeong Jin Lee

IPC: H01L21/00 ,  H01L21/66 ,  G01R31/26 ,  G03F1/44 ,  G01B11/00 ,  H01L21/027 ,  G03F1/36 ,  G03F1/42

CPC classification number: G03F1/44 ,  G01B11/005 ,  G03F1/36 ,  G03F1/42 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/0273 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30

Abstract: A method may include forming a first grating and a second grating, disposed in a region of vertical overlap of the first and second gratings on different levels, respectively, having substantially the same pitch, and inclined with respect to each other, such that a bias value between the first and second gratings is changed along a length direction of the first and second gratings, using a lithography process. A method may include emitting a beam to the first and second gratings; and obtaining trend information associated with a diffracted beam from an image pattern of a beam from the first and second gratings, using the emitted beam, in which the trend information may concern changes in the intensity of the diffracted beam according to the bias value. An overlay error in at least one grating may be determined based on the trend information and an intensity of a diffracted beam.

公开(公告)号：US09791790B2

公开(公告)日：2017-10-17

申请号：US14901541

申请日：2014-01-03

Applicant: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinmin Li ,  Junxi Wang ,  Qingfeng Kong ,  Jinxia Guo ,  Xiaoyan Yi

IPC: G03F9/00 ,  G03F1/42

CPC classification number: G03F9/7084 ,  G03F1/42

Abstract: The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.

公开(公告)号：US20170154852A1

公开(公告)日：2017-06-01

申请号：US15057406

申请日：2016-03-01

Applicant: Kabushiki Kaisha Toshiba

Inventor： Kenichi YASUDA ,  Shinya ARAI

IPC: H01L23/544 ,  H01L21/768 ,  H01L21/027 ,  H01L21/28 ,  H01L21/66 ,  H01L21/033 ,  H01L27/115

CPC classification number: H01L23/544 ,  G03F1/42 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/28282 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76877 ,  H01L22/20 ,  H01L27/11582 ,  H01L28/00 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.

公开(公告)号：US09658531B2

公开(公告)日：2017-05-23

申请号：US14475967

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Guoxiang Ning ,  Chunyu Wong ,  Paul Ackmann ,  Sarasvathi Thangaraju

IPC: G03F1/26 ,  G03F7/20 ,  G03F1/28 ,  G03F1/50 ,  G03F1/42

CPC classification number: G03F7/20 ,  G03F1/28 ,  G03F1/42 ,  G03F1/50

Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.

公开(公告)号：US09599887B2

公开(公告)日：2017-03-21

申请号：US14850835

申请日：2015-09-10

Applicant: SK hynix Inc.

Inventor： Byung Ho Nam

IPC: G03F1/42

CPC classification number: G03F1/42

Abstract: A photo mask includes a pre-alignment key used in a pre-alignment process performed in a photolithography apparatus. The pre-alignment key includes a pre-alignment pattern including a light transmitting area and a light blocking area surrounding the pre-alignment pattern. The light blocking area includes a plurality of light blocking patterns and a diffraction grating pattern separating the plurality of light blocking patterns from each other.

公开(公告)号：US20160195387A1

公开(公告)日：2016-07-07

申请号：US15054238

申请日：2016-02-26

Applicant: Carl Zeiss SMT GmbH ,  Carl Zeiss Meditec AG

Inventor： Michael Arnz ,  Dirk Seidel ,  Gerd Klose

IPC: G01B11/26

CPC classification number: G01B11/26 ,  G01B11/00 ,  G03F1/42 ,  G03F1/84

Abstract: A method for determining a registration error of a feature on a mask, including providing a first aerial image that was captured by means of a position measuring device and includes at least the feature, simulating, from pattern specifications of the mask, a second aerial image that includes at least the feature, taking into account at least one effect that causes distortion of the first aerial image, and determining the registration error of the feature as the distance of the position of the feature in the first aerial image from the position of the feature in the second aerial image. Also provided is a method for simulating an aerial image from pattern specifications of a mask and a position measuring device for carrying out the method.

Abstract translation: 一种用于确定掩模上的特征的配准误差的方法，包括提供通过位置测量装置捕获的第一空间图像，并且至少包括从掩模的图案规格模拟第二空间图像的特征 考虑到引起第一空间图像失真的至少一个效应，以及确定特征的登记误差作为第一空间图像中的特征的位置与第一空间图像的位置的距离，至少包括该特征 功能在第二个航空图像。 还提供了一种用于从掩模的图案规格和用于执行该方法的位置测量装置模拟空中图像的方法。

公开(公告)号：US09377678B2

公开(公告)日：2016-06-28

申请号：US14084773

申请日：2013-11-20

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Alan Lee ,  Xi Ge

IPC: G03F7/20 ,  G03F1/00 ,  G03F1/42

CPC classification number: G03F1/00 ,  G03F1/42 ,  G03F1/50 ,  G03F7/70283 ,  G03F7/70425

Abstract: A method of processing a semiconductor wafer may include providing a rotatably alignable photolithography mask that includes different mask images. Each mask image may be in a corresponding different mask sector. The method may also include performing a series of exposures with the rotatably alignable photolithography mask at different rotational alignments with respect to the semiconductor wafer so that the different mask images produce at least one working semiconductor wafer sector, and at least one non-working semiconductor wafer sector.

Abstract translation: 一种处理半导体晶片的方法可以包括提供包括不同掩模图像的可旋转对准的光刻掩模。 每个掩模图像可以在相应的不同的掩模扇区中。 该方法还可以包括使用相对于半导体晶片的不同旋转对准的可旋转对准的光刻掩模执行一系列曝光，使得不同的掩模图像产生至少一个工作半导体晶片扇区，以及至少一个非工作半导体晶片 部门。