公开(公告)号：US12082408B2

公开(公告)日：2024-09-03

申请号：US17481803

申请日：2021-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yuancheng Yang ,  Wenxi Zhou ,  Zhiliang Xia ,  Wei Liu

IPC: H10B41/41 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/41 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second peripheral circuit is between the bonding interface and the second semiconductor layer. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

公开(公告)号：US12080697B2

公开(公告)日：2024-09-03

申请号：US17525533

申请日：2021-11-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Shiqi Huang ,  Wei Liu ,  Bater Chelon ,  Siping Hu

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L25/18 ,  H01L23/528 ,  H01L24/03 ,  H01L24/08 ,  H01L24/09 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08112 ,  H01L2224/08146 ,  H01L2224/09181 ,  H01L2224/32147 ,  H01L2224/33181 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/14511

Abstract: Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a plurality of first NAND memory strings and a plurality of first BLs. At least one of the first BLs may be conductively connected to a respective one of the first NAND memory strings. The first semiconductor structure also includes a plurality of first conductor layers, and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers. A second semiconductor structure includes a plurality of second NAND memory strings and a plurality of second BLs.

公开(公告)号：US12033967B2

公开(公告)日：2024-07-09

申请号：US17553765

申请日：2021-12-16

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Hongbin Zhu ,  Wei Liu ,  Yanhong Wang

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, and a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the third direction and one side of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

公开(公告)号：US11955422B2

公开(公告)日：2024-04-09

申请号：US17488287

申请日：2021-09-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Lei Xue ,  Wei Liu ,  Liang Chen

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5223 ,  H01L21/76832 ,  H01L28/40 ,  H01L28/56 ,  H10B43/27 ,  H10B43/35

Abstract: Embodiments of semiconductor devices and methods for forming the same are disclosed. In an example, a semiconductor device includes at least one dielectric layer pair including a first dielectric layer and a second dielectric layer different from the first dielectric layer, an interlayer dielectric (ILD) layer in contact with the at least one dielectric layer pair, and one or more capacitors each extending vertically through the ILD layer and in contact with the at least one dielectric layer pair.

公开(公告)号：US20240098973A1

公开(公告)日：2024-03-21

申请号：US18231731

申请日：2023-08-08

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yaqin Liu ,  Wei Liu ,  Yanhong Wang ,  Shiqi Huang ,  Zichen Liu

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor device, a memory system, and a fabricating method are provided. The semiconductor device comprises a memory structure bonded with a circuit structure. The memory structure comprises: first transistors each comprising a semiconductor body extending in a vertical direction, a semiconductor layer on a lateral side of the first transistors, a first isolation structure extending through the semiconductor layer and laterally encircling a first portion of the semiconductor layer, a first contact structure extending through the first portion of the semiconductor layer, and a first contact pad above the first portion of the semiconductor layer and connected with the first contact structure. A lateral dimension of the first contact pad is less than a lateral dimension of the first portion of the semiconductor layer. The circuit structure comprises a second transistor, and the first contact pad is electrically connected to the second transistor by the first contact structure.

公开(公告)号：US20230413531A1

公开(公告)日：2023-12-21

申请号：US18220096

申请日：2023-07-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yaqin Liu ,  Yanhong Wang ,  Wei Liu

IPC: H10B12/00 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B12/33 ,  H10B12/482 ,  H10B12/036 ,  H10B12/05 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The vertical transistor is disposed between the bit line and the storage unit along the first direction.

公开(公告)号：US20230380137A1

公开(公告)日：2023-11-23

申请号：US18222898

申请日：2023-07-17

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Wei Liu ,  Hongbin Zhu ,  Yanhong Wang ,  Bingjie Yan ,  Wenyu Hua ,  Fandong Liu ,  Ya Wang

IPC: H10B12/00

CPC classification number: H10B12/0383 ,  H10B12/50

Abstract: A semiconductor device and methods for forming the same are provided. The semiconductor device includes an array of vertical transistors. Each transistor includes a semiconductor body extending in a vertical direction, and a gate structure located adjacent to a sidewall of the semiconductor body. The gate structures of each row of vertical transistors are connected with each other and extend along a first lateral direction to form a word line. A first word line of a first row of vertical transistors is located at a first side of the semiconductor bodies of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and a second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located at a second side of the semiconductor bodies of the second row of vertical transistors along the second lateral direction.

公开(公告)号：US11721609B2

公开(公告)日：2023-08-08

申请号：US17347086

申请日：2021-06-14

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Liang Chen ,  Wei Liu ,  Shao-Fu Sanford Chu

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/535

Abstract: In a method for forming an integrated structure, a top dielectric layer is formed over a top surface of a substrate. The top dielectric layer includes a plurality of vias that are formed through the top dielectric layer and extend into the substrate. A bottom dielectric layer is formed on a bottom surface of the substrate. An isolation opening and a plurality of contact openings are further formed in the bottom dielectric layer and the substrate, where the isolation opening passes through the bottom dielectric layer and extends from the bottom surface to the top surface of the substrate. The isolation opening is filled with an insulating layer to form an isolation trench. The plurality of contact openings are filled with a conductive layer to form a plurality of through silicon contacts (TSCs). A conductive plate is further formed over the bottom dielectric layer.

公开(公告)号：US11710679B2

公开(公告)日：2023-07-25

申请号：US17338231

申请日：2021-06-03

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Liang Chen ,  Wei Liu ,  Shao-Fu Sanford Chu

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/535

Abstract: In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. A second dielectric layer is formed on an opposing second main surface of the substrate. A first via is formed in the second dielectric layer, and a first end of the first via extends into the substrate to be in contact with the TSC. A second via is formed in the second dielectric layer and a first end of the second via extends into the substrate. A metal line is formed over the second dielectric layer so as to be coupled to the first via and the second via.

公开(公告)号：US20230157027A1

公开(公告)日：2023-05-18

申请号：US17846612

申请日：2022-06-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Liang Chen ,  Shiqi Huang ,  Wei Liu ,  Yanhong Wang

IPC: H01L27/11575 ,  H01L27/11582

CPC classification number: H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional (3D) memory device includes a plurality of memory stacks arranged along a first direction, and a dummy block structure disposed between two adjacent memory stacks. Each memory stack includes a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction. A channel structure extends through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction. A first isolation structure is disposed between the dummy block structure and one of the plurality of memory stacks. A substrate is disposed under the plurality of memory stacks, the dummy block structure, and the first isolation structure. A second isolation structure is disposed in the substrate extending along the second direction.