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    Enhanced puncturing and low-density parity-check (LDPC) code structure
    92.
    发明授权
    Enhanced puncturing and low-density parity-check (LDPC) code structure 有权

    公开(公告)号：US10454499B2

    公开(公告)日：2019-10-22

    申请号：US15593035

    申请日：2017-05-11

    Applicant: QUALCOMM Incorporated

    Inventor： Thomas Joseph Richardson ,  Shrinivas Kudekar

    IPC: H03M13/00 ,  H03M13/11 ,  H03M13/03

    Abstract: Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.

    Adjusted min-sum decoder
    93.
    发明授权
    Adjusted min-sum decoder 有权

    公开(公告)号：US10419027B2

    公开(公告)日：2019-09-17

    申请号：US15782807

    申请日：2017-10-12

    Applicant: QUALCOMM Incorporated

    Inventor： Thomas Joseph Richardson ,  Shrinivas Kudekar ,  Vincent Loncke

    IPC: H03M13/11 ,  H03M13/00 ,  H04W24/08 ,  H03M13/39

    Abstract: Certain aspects of the present disclosure generally relate to techniques for efficient, high-performance decoding of low-density parity check (LDPC) codes, for example, by using an adjusted minimum-sum (AdjMS) algorithm, which involves approximating an update function and determining magnitudes of outgoing log likelihood ratios (LLRs). Similar techniques may also be used for decoding turbo codes. Other aspects, embodiments, and features (such as encoding technique) are also claimed and described.

    High performance, flexible, and compact low-density parity-check (LDPC) code
    94.
    发明授权
    High performance, flexible, and compact low-density parity-check (LDPC) code 有权

    公开(公告)号：US10291354B2

    公开(公告)日：2019-05-14

    申请号：US15622008

    申请日：2017-06-13

    Applicant: QUALCOMM Incorporated

    Inventor： Thomas Joseph Richardson ,  Shrinivas Kudekar

    IPC: H04L1/00 ,  H04L1/18 ,  H03M13/03 ,  H03M13/11 ,  H03M13/00

    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.

    Techniques for use in wideband time-of-arrival estimation
    96.
    发明授权
    Techniques for use in wideband time-of-arrival estimation 有权

    公开(公告)号：US09939521B2

    公开(公告)日：2018-04-10

    申请号：US14593864

    申请日：2015-01-09

    Applicant: QUALCOMM Incorporated

    Inventor： Jubin Jose ,  Xinzhou Wu ,  Thomas Joseph Richardson

    IPC: H04W52/54 ,  G01S11/06 ,  H04L27/26 ,  H04W52/32 ,  H04B17/27 ,  H04W52/16

    CPC classification number: G01S11/06 ,  H04B17/27 ,  H04L27/26 ,  H04W52/16 ,  H04W52/325 ,  H04W52/54

    Abstract: Provided are apparatus and methods for ranging between a plurality of wireless devices. An exemplary method includes, at a first wireless device, transmitting a primary portion symbol comprising a first packet and transmitting a secondary portion symbol. The secondary portion symbol is transmitted simultaneously at a lower transmit power than the primary portion symbol, and the secondary portion symbol comprises a second packet identical to the first packet. The primary portion symbol can be transmitted in a first channel having a substantially 20 MHZ bandwidth and the secondary portion can be transmitted in a second channel having a substantially 20 MHZ bandwidth. The first and second channels are substantially adjacent in frequency. After transmitting the primary portion symbol, for example, a high-throughput long-training-field symbol or a very-high-throughput long-training-field symbol can be repetitively transmitted. This exemplary method enhances time-of-arrival estimation accuracy, minimizes decoding bottlenecking, and maximizes wireless device range.

    INTERLACING METHOD FOR HIGH THROUGHPUT FORWARD ERROR CORRECTION
    97.
    发明申请
    INTERLACING METHOD FOR HIGH THROUGHPUT FORWARD ERROR CORRECTION 审中-公开

    公开(公告)号：US20170180079A1

    公开(公告)日：2017-06-22

    申请号：US15377707

    申请日：2016-12-13

    Applicant: QUALCOMM Incorporated

    Inventor： Thomas Joseph Richardson ,  Vincent Abayomi Loncke

    IPC: H04L1/00

    CPC classification number: H04L1/0061 ,  H03M13/27 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0065 ,  H04L1/0071

    Abstract: Encoders, decoders and methods of encoding and decoding data can comprise receiving source symbols in a first sequence, storing the source symbols to a first memory in a second sequence, wherein the first sequence is a first interlacing relative to the second sequence, determining if the memory contains all source symbols of a codeword, wherein the source symbols of a codeword are the symbols used to generate repair symbols for that codeword, generating repair symbols for the codeword, storing the repair symbols to a second memory in a third sequence, interlacing the repair symbols and the source symbols into an output stream as a stream of encoded symbols, wherein the repair symbols appear in the output stream in a fourth sequence, wherein the fourth sequence is a second interlacing relative to the third sequence, and outputting the stream of encoded symbols.

    Methods and apparatus for enabling distributed frequency synchronization
    98.
    发明授权
    Methods and apparatus for enabling distributed frequency synchronization 有权

    公开(公告)号：US09621289B2

    公开(公告)日：2017-04-11

    申请号：US14586523

    申请日：2014-12-30

    Applicant: QUALCOMM Incorporated

    Inventor： Saurabha Rangrao Tavildar ,  Thomas Joseph Richardson ,  Junyi Li

    IPC: H04J3/06 ,  H04W56/00

    CPC classification number: H04J3/0664 ,  H04J3/0641 ,  H04W56/00 ,  H04W56/0015 ,  H04W56/0035

    Abstract: A method, an apparatus, and a computer program product for wireless communication are provided in connection with enabling distributed frequency synchronization based on a fastest node clock rate. In one example, a first UE is equipped to determine that a fastest clock rate is faster than an internal clock rate of the first UE by more than a first positive offset, and adjust the internal clock rate based on the determined fastest clock rate. In an aspect, the fastest clock rate is associated with a second UE of one or more other UEs from which synchronization signals may be received. In another example, a UE is equipped to obtain GPS based timing information, adjust an internal clock rate based on the GPS based timing information, and transmit a synchronization signal at an artificially earlier time in comparison to a scheduled time of transmission associated with the adjusted internal clock rate.

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