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公开(公告)号：US11488651B2
公开(公告)日：2022-11-01
申请号：US17135403
申请日：2020-12-28
IPC分类号： G11C11/406 , G11C11/403 , G11C11/408
摘要： A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.
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公开(公告)号：US11410713B2
公开(公告)日：2022-08-09
申请号：US16840946
申请日：2020-04-06
发明人： Di Wu , Debra M. Bell , Anthony D. Veches , James S. Rehmeyer , Libo Wang
IPC分类号： G11C7/22 , G11C7/10 , G11C8/10 , G11C11/4096 , G11C11/4076 , G11C11/406
摘要： Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.
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公开(公告)号：US20220189540A1
公开(公告)日：2022-06-16
申请号：US17684235
申请日：2022-03-01
发明人： Dale H. Hiscock , Debra M. Bell , Michael Kaminski , Joshua E. Alzheimer , Anthony D. Veches , James S. Rehmeyer
IPC分类号： G11C11/406 , G11C11/4074 , G11C16/10 , G11C11/4072
摘要： Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.
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94.发明申请公开(公告)号：US20220148638A1
公开(公告)日：2022-05-12
申请号：US17094731
申请日：2020-11-10
IPC分类号： G11C11/406 , G11C11/4074 , G11C11/4076
摘要： Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.
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公开(公告)号：US20220093488A1
公开(公告)日：2022-03-24
申请号：US17030144
申请日：2020-09-23
IPC分类号： H01L23/467 , H01L25/00 , H01L25/10
摘要： An improved memory module and methods for constructing the same are disclosed herein. The memory module includes a substrate having a first surface and a second surface opposite the first surface, each having a central portion, a first array area and a second array area. The first array area is cooler than the second array area during operation. The memory module also includes a power management integrated circuit attached to the central portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array area. The first semiconductor die has a first performance rating of an operating parameter at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array area. The second semiconductor die has a second performance rating of an operating parameter better than the first performance rating at high temperatures.
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公开(公告)号：US11222683B2
公开(公告)日：2022-01-11
申请号：US17008396
申请日：2020-08-31
发明人： James S. Rehmeyer
IPC分类号： G11C11/406 , G11C8/12 , G11C11/4076 , G11C11/408
摘要： Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of targeted refresh operations. Memory dies may need to periodically perform refresh operations, which may be auto-refresh operations or targeted refresh operations. Targeted refresh operations may draw less current than auto-refresh operations. When dies are collected into a group (e.g., a memory stack, a memory module) the timing of targeted refresh operations may be staggered between the different dies to help reduce the peak current drawn. The targeted refresh operations may be staggered such that, when a maximum number of the dies are performing a refresh operation, at least one of the dies performs a targeted refresh operation instead of an auto-refresh operation.
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公开(公告)号：US20220005523A1
公开(公告)日：2022-01-06
申请号：US16921729
申请日：2020-07-06
IPC分类号： G11C11/406 , G06F11/30
摘要： Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.
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公开(公告)号：US20210398603A1
公开(公告)日：2021-12-23
申请号：US17466160
申请日：2021-09-03
摘要： Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.
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公开(公告)号：US20210263847A1
公开(公告)日：2021-08-26
申请号：US16800356
申请日：2020-02-25
发明人： James S. Rehmeyer , Libo Wang , Anthony D. Veches , Debra M. Bell , Di Wu
IPC分类号： G06F12/06 , G06F11/10 , G06F16/2455
摘要： Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data may be retrieved from a memory array for the pattern matching operation by a read operation, a refresh operation, an error correction operation, and/or a pattern matching operation. The data may be retrieved from incoming data input lines instead of or in addition to the memory array. How the data is stored or retrieved for pattern matching operations may be controlled by a memory controller.
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公开(公告)号：US20210225431A1
公开(公告)日：2021-07-22
申请号：US17226975
申请日：2021-04-09
IPC分类号： G11C11/406 , H01L25/065
摘要： Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto-refresh operations may be periodically skipped when charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency. To reduce peak current draw during refresh operations, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operation may be staggered in time among memory dies of the memory to limit a number of memory dies that are performing an auto-refresh operation to a maximum number. In another example, the skipped refresh operation may be staggered in time among memory banks of a single memory array to limit a number of memory banks that are performing an auto-refresh operation to a maximum number.
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