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    Delay locked loop
    91.
    发明申请
    Delay locked loop 失效

    公开(公告)号：US20070046347A1

    公开(公告)日：2007-03-01

    申请号：US11323912

    申请日：2005-12-29

    Applicant: Hyun-Woo Lee

    Inventor： Hyun-Woo Lee

    IPC: H03L7/06

    CPC classification number: H03L7/0814 ,  H03L7/0818 ,  H03L7/087

    Abstract: A DLL for reducing jitter during a high frequency operation by separately controlling a coarse delay and a fine delay. The DLL includes a multiplexing unit for selectively outputting one of the rising clock and the falling clock; a first delay line for generating a first internal clock and a second internal clock; a second delay line for generating a first clock and a second clock; a delay line control unit for controlling the second delay line; a phase control unit for generating a first DLL clock and a second DLL clock by mixing the first clock and the second clock; and a phase comparing unit for comparing the first DLL clock and the second DLL clock with the rising clock to generate a lock signal for controlling an operation timing of the first delay line and the second delay line.

    Digital delay locked loop capable of correcting duty cycle and its method
    92.
    发明授权
    Digital delay locked loop capable of correcting duty cycle and its method 有权

    公开(公告)号：US07161397B2

    公开(公告)日：2007-01-09

    申请号：US11020491

    申请日：2004-12-21

    Applicant: Hyun-Woo Lee ,  Jong-Tae Kwak

    Inventor： Hyun-Woo Lee ,  Jong-Tae Kwak

    IPC: H03L7/06

    CPC classification number: H03K5/1565

    Abstract: An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.

    Apparatus and method for coding/decoding TFCI bits in an asynchronous CDMA communication system
    95.
    发明授权
    Apparatus and method for coding/decoding TFCI bits in an asynchronous CDMA communication system 有权
    在异步CDMA通信系统中对TFCI位进行编码/解码的装置和方法

    公开(公告)号：US07088700B2

    公开(公告)日：2006-08-08

    申请号：US09974656

    申请日：2001-10-09

    Applicant: Hyun-Woo Lee ,  Jae-Yoel Kim ,  Sung-Ho Choi ,  Kyeong-Cheol Yang

    Inventor： Hyun-Woo Lee ,  Jae-Yoel Kim ,  Sung-Ho Choi ,  Kyeong-Cheol Yang

    IPC: H04B7/216

    CPC classification number: H04L1/0069 ,  H04B1/707 ,  H04L1/0009 ,  H04L1/0025 ,  H04L1/0039 ,  H04L1/0072 ,  H04L1/0091 ,  H04W48/08

    Abstract: Disclosed is an apparatus for encoding TFCI bits in an asynchronous CDMA mobile communication system including a UE and a Node B for transmitting packet data to the UE. A TFCI bit generator creates the TFCI bits, the number of which is variable depending on an information bit ratio of the first channel to the second channel. A code length information generator generates code length information for setting a length of a codeword according to the information bit ratio. A Walsh code generator generates first to fifth basis Walsh codewords. A sequence generator generates an all-1 sequence. A mask generator generates first to fourth basis masks. First to tenth multipliers multiply the TFCI bits by the first to fifth basis Walsh codewords, the all-1 sequence and the first to fourth basis masks, respectively. An adder adds outputs of the first to tenth multipliers. A puncturer punctures a codeword output from the adder according to the code length information.

    Abstract translation: 公开了一种用于编码包括UE和用于向UE发送分组数据的节点B的异步CDMA移动通信系统中的TFCI比特的装置。 TFCI位生成器创建TFCI位，其数量根据第一通道与第二通道的信息比特率而变化。 码长信息生成器生成用于根据信息比特率设置码字的长度的码长信息。 沃尔什码发生器产生第一到第五基准沃尔什码字。 序列发生器生成一个全序列。 掩模发生器产生第一至第四基准掩模。 第一至第十乘法器将TFCI比特分别乘以第一至第五基准沃尔什码字，全序列和第一至第四基本掩码。 加法器将第一至第十乘法器的输出相加。 穿刺器根据码长度信息来刺穿从加法器输出的码字。

    Delay locked loop for use in semiconductor memory device and method thereof
    97.
    发明申请
    Delay locked loop for use in semiconductor memory device and method thereof 有权
    延迟锁定环用于半导体存储器件及其方法

    公开(公告)号：US20060132203A1

    公开(公告)日：2006-06-22

    申请号：US11144474

    申请日：2005-06-02

    Applicant: Hyun-Woo Lee

    Inventor： Hyun-Woo Lee

    IPC: H03L7/06

    CPC classification number: H03L7/0814 ,  H03L7/089

    Abstract: A delay locked loop (DLL) for generating a delay locked clock signal includes a delay line unit for delaying an external clock signal according to a delay amount control signal to thereby generate the delay locked clock signal; a divider for dividing the delay locked clock signal by a predetermined number determined based on a column address strobe (CAS) latency to thereby generate a divided signal; and a delay line control unit for generating the delay amount control signal based on a result of comparing a phase of the external clock signal and a delayed signal of the divided signal.

    Abstract translation: 用于产生延迟锁定时钟信号的延迟锁定环（DLL）包括延迟线单元，用于根据延迟量控制信号延迟外部时钟信号，从而产生延迟锁定时钟信号; 分频器，用于将延迟锁定时钟信号除以基于列地址选通（CAS）等待时间确定的预定数量，从而产生分频信号; 以及延迟线控制单元，用于基于将外部时钟信号的相位与分频信号的延迟信号进行比较的结果来产生延迟量控制信号。

    Apparatus and method for gating data on a control channel in a CDMA communication system
    99.
    发明授权
    Apparatus and method for gating data on a control channel in a CDMA communication system 有权
    用于在CDMA通信系统中的控制信道上门控数据的装置和方法

    公开(公告)号：US07006482B1

    公开(公告)日：2006-02-28

    申请号：US09677342

    申请日：2000-10-02

    Applicant: Ho-Kyu Choi ,  Chang-Soo Park ,  Sung-Oh Hwang ,  Hyun-Woo Lee ,  Jae-Min Ahn ,  Youn-Sun Kim ,  Hi-Chan Moon ,  Seong-ill Park

    Inventor： Ho-Kyu Choi ,  Chang-Soo Park ,  Sung-Oh Hwang ,  Hyun-Woo Lee ,  Jae-Min Ahn ,  Youn-Sun Kim ,  Hi-Chan Moon ,  Seong-ill Park

    IPC: H04B7/216

    CPC classification number: H04W52/56 ,  H04B2201/70709 ,  H04J13/00 ,  H04W52/16 ,  H04W52/44 ,  H04W52/58

    Abstract: A method for transmitting control data on a downlink and/or uplink channel in a base station and/or mobile station in a mobile communication system. In one embodiment, the base station determines whether there is downlink channel data to transmit to a mobile station. If there is no data to be transmitted over the downlink channel for a predetermined time period, the base station drives a random gating position selector to determine a random gating slot position, gates on the control data at the determined slot position, and gates off the control data at other slot positions. The random position selector determines the gating slot position by calculating a value x by multiplying a system frame number (SFN) of a received signal by a specific integer; selecting n bits starting from a position which is at an x-chip distance from the start point of a scrambling code, which has a period equal to one frame, before a plurality of gating durations used in generating a downlink signal; and determining a gating slot position of a corresponding gating slot group by performing a modulo operation on the selected n bits, where the module operation is by the number of slots in a gating slot group.

    Abstract translation: 一种用于在移动通信系统中的基站和/或移动台中的下行链路和/或上行链路信道上发送控制数据的方法。 在一个实施例中，基站确定是否存在要向移动台发送的下行链路信道数据。 如果在预定时间段内没有要通过下行链路信道发送的数据，则基站驱动随机门控位置选择器以确定随机门控时隙位置，在所确定的时隙位置对控制数据进行门控，并关闭 在其他插槽位置控制数据。 随机位置选择器通过将接收信号的系统帧号（SFN）乘以特定整数来计算值x来确定选通时隙位置; 在用于生成下行链路信号的多个选通持续时间之前，从具有周期等于一帧的扰码开始点处的x码片距离的位置开始选择n个比特; 以及通过对所选择的n位执行模运算来确定对应的门控时隙组的门控时隙位置，其中模块操作是通过门控时隙组中的时隙数量。

    Apparatus and method for coding/decoding optimal (11,5) codeword in a mobile communication system
    100.
    发明授权
    Apparatus and method for coding/decoding optimal (11,5) codeword in a mobile communication system 有权
    用于在移动通信系统中编码/解码最优（11,5）码字的装置和方法

    公开(公告)号：US06961387B2

    公开(公告)日：2005-11-01

    申请号：US09957967

    申请日：2001-09-21

    Applicant: Jae-Yoel Kim ,  Hyun-Woo Lee ,  Kook-Heui Lee

    Inventor： Jae-Yoel Kim ,  Hyun-Woo Lee ,  Kook-Heui Lee

    IPC: H04J11/00 ,  H04L1/00 ,  H04L23/02 ,  H04L5/12

    CPC classification number: H04L1/0057 ,  H04J13/004 ,  H04J13/12 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0069 ,  H04L1/0072

    Abstract: An apparatus encodes an input information bit stream comprised of 5 bits into a (11,5) codeword comprised of 11 coded symbols. The apparatus comprises a Reed-Muller encoder for encoding the input information bit stream into a first order Reed-Muller codeword comprised of 16 coded symbols; and a puncturer for selecting a second coded symbol position or a third coded symbol position out of the 16 coded symbols constituting the first order Reed-Muller codeword, puncturing the coded symbols at intervals of 3 symbols beginning at the selected position, and thus outputting an optimal (11,5) codeword.

    Abstract translation: 一种装置将由5比特组成的输入信息比特流编码成由11个编码符号组成的（11,5）码字。 该装置包括用于将输入信息比特流编码成由16个编码符号组成的一阶里德 - 穆勒码字的里德 - 穆勒编码器; 以及一个穿孔器，用于从构成一阶里德 - 穆勒码字的16个编码符号中选择第二编码符号位置或第三编码符号位置，以从所选择的位置开始的3个符号间隔进行穿孔，从而输出 最优（11,5）码字。

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