公开(公告)号：US10922553B2

公开(公告)日：2021-02-16

申请号：US16379176

申请日：2019-04-09

Applicant: Intel Corporation

Inventor： Mayuresh M. Varerkar ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Sherine Abdelhak ,  Sachin Godse ,  Farshad Akhbari ,  Narayan Srinivasa ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Dukhwan Kim ,  Feng Chen ,  Abhishek R. Appu ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: H04N5/225 ,  H04N3/20 ,  H04N5/228 ,  G06K9/00 ,  G06T1/20 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  H04N7/14 ,  H04N5/38

Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

公开(公告)号：US20200342321A1

公开(公告)日：2020-10-29

申请号：US16957056

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Arnab Paul ,  Narayan Srinivasa

IPC: G06N3/08 ,  G06N3/04

Abstract: Techniques and mechanisms for performing a Bayesian inference with a spiking neural network. In an embodiment, a parent node of the spiking neural network receives a first bias signal which is periodic. The parent node communicates a likelihood signal to a child node, wherein the parent node and the child node correspond to a first condition and a second condition, respectively. Based on a phase change which is applied to the first bias signal, the likelihood signal indicates a probability of the first condition. The child node also receives a signal which indicates an instance of the second condition. Based on the indication and a second bias signal, the child node signals to the first node that an adjustment is to be made to the phase change applied to the first bias signal. After the adjustment, the likelihood signal indicates an updated probability of the first condition.

公开(公告)号：US20200265290A1

公开(公告)日：2020-08-20

申请号：US16648169

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Arnab Paul ,  Narayan Srinivasa

IPC: G06N3/04 ,  G06N3/08

Abstract: Techniques and mechanisms for providing a logical state machine with a spiking neural network which includes multiple sets of nodes. Each of the multiple sets of nodes is to implement a different respective state, and each of the multiple spike trains is provided to respective nodes of each of the multiple sets of nodes. A given state of the logical state machine is implemented by configuring respective activation modes of each node of the corresponding set of nodes. The activation mode of a given node enables that node to signal, responsive to its corresponding spike train, that a respective state transition of the logical state machine is to be performed. In another embodiment, the multiple spike trains each represent a different respective character in a system used by data evaluated with the spiking neural network.

公开(公告)号：US20200218959A1

公开(公告)日：2020-07-09

申请号：US16644446

申请日：2017-12-19

Applicant: Intel Corporation

Inventor： Narayan Srinivasa

IPC: G06N3/04 ,  G06N3/08 ,  G06K9/00 ,  G06K9/62

Abstract: Techniques and mechanisms for processing differential video data with a spiking neural network to provide action recognition functionality. In an embodiment, the spiking neural network is coupled to receive and process a first one or more spike trains which represent an encoded version of a sequence comprising frames of differential video data. In turn, the frames of differential video data are each based on a difference between a respective two frames of raw video data. Based on the processing of the first one or more spike trains, the spiking neural network may output a second one or more spike trains. In another embodiment, the second one or more spike trains are provided to train the spiked neural network to recognize an activity type, or to classify a video sequence as including a representation of an instance of the activity type.

公开(公告)号：US10540318B2

公开(公告)日：2020-01-21

申请号：US15482796

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC: G06F13/40 ,  G06T1/20 ,  G06F13/00 ,  G06F9/30 ,  G06F15/80 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US20200019401A1

公开(公告)日：2020-01-16

申请号：US16444188

申请日：2019-06-18

Applicant: Intel Corporation

Inventor： Feng Chen ,  Narayan Srinivasa ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Joydeep Ray ,  Nicolas C. Galoppo Von Borries ,  Prasoonkumar Surti ,  Ben J. Ashbaugh ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0862 ,  G06F9/50

Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.

公开(公告)号：US10417731B2

公开(公告)日：2019-09-17

申请号：US15494886

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F8/41

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.

公开(公告)号：US20190243764A1

公开(公告)日：2019-08-08

申请号：US16277267

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Prasoonkumar Surti ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Abhishek R. Appu ,  Nicolas C. Galoppo Von Borries ,  Joydeep Ray ,  Narayan Srinivasa ,  Feng Chen ,  Ben J. Ashbaugh ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0837 ,  G06N20/00 ,  G06T1/20 ,  G06N3/08

CPC classification number: G06F12/0837 ,  G06F12/0815 ,  G06F2212/62 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084 ,  G06N3/088 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

公开(公告)号：US10341669B2

公开(公告)日：2019-07-02

申请号：US15385125

申请日：2016-12-20

Applicant: Intel Corporation

Inventor： Chit Kwan Lin ,  Gautham N Chinya ,  Narayan Srinivasa

IPC: H04N19/182 ,  G06N3/04 ,  G06K9/62 ,  H04N19/129

Abstract: System and techniques for temporally encoded static spatial images are described herein. A static spatial image may be obtained. Here, the static spatial image defines pixel values over an area. A scan path may be selected. Here, the scan path defines a path across the area of the static spatial image. A window is scanned (e.g., moved or slid) along the scan path on the static spatial image to produce changes in a portion of the window over time. The changes in the portion of the window are recorded along with respective times of the changes.

公开(公告)号：US10255656B2

公开(公告)日：2019-04-09

申请号：US15798574

申请日：2017-10-31

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

IPC: G06T1/20 ,  G06T15/04 ,  G06T15/00 ,  G09G5/36 ,  G06F9/38

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.