公开(公告)号：US08173802B2

公开(公告)日：2012-05-08

申请号：US12311315

申请日：2007-10-10

Applicant: Hirohito Oooka ,  Yasushi Shibata ,  Hiroki Inoue ,  Tsutomu Imagawa

Inventor： Hirohito Oooka ,  Yasushi Shibata ,  Hiroki Inoue ,  Tsutomu Imagawa

IPC: C07D471/08

CPC classification number: C07D221/22 ,  C07D221/24 ,  C07D491/113

Abstract: Provided is a method for producing a piperidin-4-one derivative useful as an intermediate for agricultural chemicals or pharmaceutical products. A piperidin-4-one derivative represented by formula (III-a) or formula (III-b) is produced by reacting a cyclic bis(aminol)ether compound represented by formula (I) and an acetone derivative represented by formula (II) in the presence of at least one substance selected from the group consisting of protonic acids, Lewis acids, acid halides and dialkyl sulfuric acids.

Abstract translation: 提供可用作农药或药品的中间体的哌啶-4-酮衍生物的制造方法。 由式（I-a）或式（III-b）表示的哌啶-4-酮衍生物通过式（I）表示的环状双（氨基醇）醚化合物与由式（II）表示的丙酮衍生物反应制备， 在至少一种选自质子酸，路易斯酸，酰卤和二烷基硫酸的物质存在下进行。

公开(公告)号：US08134355B2

公开(公告)日：2012-03-13

申请号：US12571938

申请日：2009-10-01

Applicant: Hiroki Inoue ,  Kei Takahashi

Inventor： Hiroki Inoue ,  Kei Takahashi

IPC: G05F3/26 ,  G05F3/28

CPC classification number: G05F3/24 ,  G06K19/0701 ,  G06K19/07749

Abstract: A semiconductor device monitors a voltage between a reference potential and an input potential and obtains a constant output potential regardless of a value of the voltage, after the voltage exceeds a predetermined threshold voltage in such a manner that the semiconductor device divides a voltage between the reference potential and the input potential using a plurality of first non-linear elements and at least one linear element to constantly generate a first bias voltage regardless of a value of the voltage, divides a voltage between the reference potential and the input potential using a plurality of second non-linear elements with reference to the first bias voltage to constantly generate a second bias voltage regardless of a value of the voltage, and determines the output potential with reference to the second bias voltage.

Abstract translation: 半导体器件监视参考电位和输入电位之间的电压，并且在电压超过预定阈值电压之后，获得恒定的输出电位，而不管电压值如何，使得半导体器件将参考电压 使用多个第一非线性元件和至少一个线性元件的电位和输入电位以恒定地产生第一偏置电压而不管电压的值，使用多个第一非线性元件和多个第一非线性元件来分配参考电位和输入电位之间的电压 参考第一偏置电压的第二非线性元件，以恒定地产生第二偏置电压，而不管电压的值，并且参考第二偏置电压确定输出电位。

公开(公告)号：US20120033510A1

公开(公告)日：2012-02-09

申请号：US13197839

申请日：2011-08-04

Applicant: Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Kiyoshi Kato

Inventor： Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Kiyoshi Kato

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C11/403 ,  G11C11/4087 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

Abstract: An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in of state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided.

Abstract translation: 目的是提供具有新颖结构的半导体器件，其即使在不提供电力且具有无限数量的写周期的情况下也可以保存存储的数据。 使用包括诸如氧化物半导体的宽带隙半导体的存储单元形成半导体器件。 半导体器件包括具有输出低于用于从存储单元读取数据的参考电位的电位的功能的电位变化电路。 当使用允许存储单元中包括的晶体管的状态电流充分降低的宽带隙半导体时，可以提供能够长期保存数据的半导体器件。

公开(公告)号：US20120014157A1

公开(公告)日：2012-01-19

申请号：US13175090

申请日：2011-07-01

Applicant: Kiyoshi Kato ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Shuhei Nagatsuka

Inventor： Kiyoshi Kato ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Shuhei Nagatsuka

IPC: G11C5/06

CPC classification number: H01L27/1156 ,  G11C11/404 ,  G11C16/0441 ,  H01L27/1207

Abstract: A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first channel formation region. The second transistor includes a second channel formation region. The first channel formation region includes a semiconductor material different from the semiconductor material of the second channel formation region.

Abstract translation: 包括在存储单元阵列中的多个存储单元被分成多个块，每个多行。 公共位线通过块中的选择晶体管电连接到分割位线。 一个存储单元包括第一晶体管，第二晶体管和电容器。 第一晶体管包括第一沟道形成区。 第二晶体管包括第二沟道形成区域。 第一沟道形成区域包括与第二沟道形成区域的半导体材料不同的半导体材料。

公开(公告)号：US20120009761A1

公开(公告)日：2012-01-12

申请号：US13256991

申请日：2010-09-28

Applicant: Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

Inventor： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

IPC: H01L21/306 ,  H01L21/304

CPC classification number: C30B29/36 ,  C30B33/06

Abstract: At least one single crystal substrate, each having a backside surface and made of silicon carbide, and a supporting portion having a main surface and made of silicon carbide, are prepared. In this preparing step, at least one of the backside surface and main surface is formed by machining. By this forming step, a surface layer having distortion in the crystal structure is formed on at least one of the backside surface and main surface. The surface layer is removed at least partially. Following this removing step, the backside surface and main surface are connected to each other.

Abstract translation: 制备至少一个具有背面并由碳化硅制成的单晶基板和具有主表面并由碳化硅制成的支撑部分。 在该制备步骤中，通过机械加工形成背面和主表面中的至少一个。 通过该形成步骤，在背面和主面中的至少一个上形成有晶体结构变形的表层。 表面层至少部分去除。 在该去除步骤之后，背面和主表面彼此连接。

公开(公告)号：US20110306181A1

公开(公告)日：2011-12-15

申请号：US13202437

申请日：2010-09-28

Applicant: Makoto Sasaki ,  Shin Harada ,  Taro Nishiguchi ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa

Inventor： Makoto Sasaki ,  Shin Harada ,  Taro Nishiguchi ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa

IPC: H01L21/762

CPC classification number: H01L29/7802 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/2007 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

Abstract: A method of manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate formed of silicon carbide and a SiC substrate formed of single crystal silicon carbide; fabricating a stacked substrate by stacking the base substrate and the SiC substrate to have their main surfaces in contact with each other; heating the stacked substrate to join the base substrate and the SiC substrate and thereby fabricating a joined substrate; and heating the joined substrate such that a temperature difference is formed between the base substrate and the SiC substrate, and thereby discharging voids formed at the step of fabricating the joined substrate at an interface between the base substrate and the SiC substrate to the outside.

Abstract translation: 制造碳化硅衬底的方法包括以下步骤：制备由碳化硅形成的基底衬底和由单晶碳化硅形成的SiC衬底; 通过堆叠基底基板和SiC基板以使它们的主表面彼此接触来制造堆叠的基板; 加热堆叠的基板以连接基底基板和SiC基板，从而制造接合的基板; 并且加热接合的基板，使得在基底基板和SiC基板之间形成温度差，从而将在基底基板和SiC基板之间的界面处制造接合基板的步骤中形成的空隙排出到外部。

公开(公告)号：US20110275224A1

公开(公告)日：2011-11-10

申请号：US13100527

申请日：2011-05-04

Applicant: Shin HARADA ,  Makoto Sasaki ,  Hiroki Inoue

Inventor： Shin HARADA ,  Makoto Sasaki ,  Hiroki Inoue

IPC: H01L21/3105

CPC classification number: H01L29/7802 ,  B32B38/0008 ,  B32B38/10 ,  B32B2313/04 ,  B32B2457/08 ,  C30B29/36 ,  H01L21/02002 ,  H01L21/187 ,  H01L29/1608 ,  H01L29/66068

Abstract: A material substrate is prepared which has a first surface and a second surface opposite to each other in a thickness direction and is made of silicon carbide. The material substrate is partially carbonized to divide the material substrate into a carbonized portion made of a material obtained by carbonizing silicon carbide, and a silicon carbide portion made of silicon carbide. This step of partially carbonizing the material substrate is performed to partially carbonize the second surface. In order to adjust a shape of the material substrate when viewed in a planar view, a portion of the material substrate is removed. This step of removing the portion of the material substrate includes the step of processing the carbonized portion. Accordingly, a silicon carbide substrate having a desired planar shape can be obtained readily.

Abstract translation: 制备材料基板，其具有在厚度方向上彼此相对的第一表面和第二表面，并且由碳化硅制成。 材料基板被部分碳化，以将材料基板分成由碳化碳化碳获得的材料制成的碳化部分和由碳化硅制成的碳化硅部分。 进行部分碳化材料基板的步骤以使第二表面部分碳化。 为了在平面图中观察时调整材料基板的形状，材料基板的一部分被去除。 去除材料基板的该部分的步骤包括处理碳化部分的步骤。 因此，可以容易地获得具有期望的平面形状的碳化硅衬底。

公开(公告)号：US20110262680A1

公开(公告)日：2011-10-27

申请号：US13093116

申请日：2011-04-25

Applicant: Taro Nishiguchi ,  Shin Harada ,  Hiroki Inoue ,  Makoto Sasaki

Inventor： Taro Nishiguchi ,  Shin Harada ,  Hiroki Inoue ,  Makoto Sasaki

IPC: C30B23/02 ,  B32B3/14

CPC classification number: H01L29/7802 ,  C30B23/02 ,  C30B29/36 ,  H01L21/02002 ,  H01L29/1608 ,  H01L29/66068

Abstract: A sublimation preventing layer is formed to cover a first region of a main surface of a material substrate. First and second single-crystal layers are arranged on the material substrate such that a gap between first and second side surfaces is located over the sublimation preventing layer. The material substrate and the first and second single-crystal layers are heated to sublimate silicon carbide from a second region of the main surface and recrystallize the sublimated silicon carbide on the first backside surface of the first single-crystal layer and the second backside surface of the second single-crystal layer, thereby forming a base substrate connected to each of the first and second backside surfaces. This can prevent formation of voids in a silicon carbide substrate having such a plurality of single-crystal layers.

Abstract translation: 形成升华防止层以覆盖材料基板的主表面的第一区域。 第一和第二单晶层布置在材料基板上，使得第一和第二侧表面之间的间隙位于升华防止层的上方。 加热材料基板和第一和第二单晶层从主表面的第二区域升华碳化硅，并将第一单晶层的第一背面上的升华的碳化硅和第一单晶层的第二背面 第二单晶层，从而形成连接到第一和第二背面中的每一个的基底基板。 这可以防止在具有多个单晶层的碳化硅衬底中形成空隙。

公开(公告)号：US20110025287A1

公开(公告)日：2011-02-03

申请号：US12843482

申请日：2010-07-26

Applicant: Hiroki Inoue

Inventor： Hiroki Inoue

IPC: G05F1/10

CPC classification number: G05F1/575

Abstract: An object of the present invention is to reduce variations in the value of the output potential VDD of a regulator circuit including a bias circuit referring threshold voltage. The regulator circuit includes a bias circuit referring threshold voltage, an error amplifier, an output control circuit, and a feedback voltage divider. Further, the regulator circuit uses an n-type transistor and p-type transistor which offer small variations in the value obtained by Vthn+|Vthp|. The feedback voltage divider includes a diode-connected p-type transistor. The increase in the threshold voltage Vthn of n-type transistors leads to the increase in the threshold voltage Vthp of the p-type transistor. Therefore, the on resistance of the p-type transistor is reduced. As a result, the fluctuations in the output potential VDD is suppressed.

Abstract translation: 本发明的目的是减少包括偏置电路参考阈值电压的调节器电路的输出电位VDD的值的变化。 调节器电路包括参考阈值电压的偏置电路，误差放大器，输出控制电路和反馈分压器。 此外，调节器电路使用提供通过Vthn + | Vthp |获得的值的小变化的n型晶体管和p型晶体管。 反馈分压器包括二极管连接的p型晶体管。 n型晶体管的阈值电压Vthn的增加导致p型晶体管的阈值电压Vthp的增加。 因此，p型晶体管的导通电阻降低。 结果，抑制了输出电位VDD的波动。

公开(公告)号：US20100165389A1

公开(公告)日：2010-07-01

申请号：US12637185

申请日：2009-12-14

Applicant: Daisuke KIDO ,  Hiroki Inoue

Inventor： Daisuke KIDO ,  Hiroki Inoue

IPC: G06F3/12 ,  G06F3/02

CPC classification number: G07C9/00103 ,  G07C11/00

Abstract: In a reception management apparatus, when a print button is operated after scheduled visitor information is selected, a badge ID representing print number is assigned to the selected scheduled visitor information and thereby print data of an entry pass associated with the scheduled visitor information is created and output to a printer. At the same time, the badge ID is assigned to and displayed in the scheduled visitor information in the appointment list display window. Further, when a shared button is operated after the scheduled visitor information is selected, the badge ID representing print number is assigned to the selected scheduled visitor information and thereby print data of the entry pass associated with the scheduled visitor information is created and output to the printer. At the same time, the personal information corresponding to the scheduled visitor information is stored in the entry-permitted list as entry-permitted visitor information.

Abstract translation: 在接收管理装置中，当选择了预约的访问者信息之后，当打印按钮被操作时，将表示打印编号的标识ID分配给所选择的预定访问者信息，从而创建与调度的访问者信息相关联的入口传递的数据， 输出到打印机。 同时，在约会列表显示窗口中分配到并显示在预定访问者信息中的徽章ID。 此外，当在所选择的预定访问者信息被选择之后操作共享按钮时，将表示打印编号的标识ID分配给所选择的预定访问者信息，从而创建与所调度的访问者信息相关联的入口传递的打印数据并将其输出到 打印机。 同时，将与预约的访问者信息相对应的个人信息作为入场许可访问者信息存储在入口许可列表中。