公开(公告)号：US08643191B2

公开(公告)日：2014-02-04

申请号：US13358792

申请日：2012-01-26

申请人： Hanyi Ding ,  Pinping Sun ,  Guoan Wang ,  Wayne H. Woods, Jr.

发明人： Hanyi Ding ,  Pinping Sun ,  Guoan Wang ,  Wayne H. Woods, Jr.

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/481 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

摘要： Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.

摘要翻译： 公开了具有功率分配器/组合器的芯片，包括芯片的模块和相关联的方法。 分隔器/组合器包括在衬底的相对侧上的第一和第二金属层。 互连件延伸穿过衬底并且包括：第一互连，围绕第一互连环形布置的第二互连和围绕第二互连环形布置的第三互连。 每个互连包括一个或多个内衬/填充有导体的通孔硅通孔。 对于功率分配器，第一互连处的第一金属层中的开口包括用于接收功率的输入端口，并且在第二互连处的第一或第二金属层中的开口包括用于向其它器件施加电力的输出端口。 对于功率组合器，在第二互连处的第一或第二金属层中的开口包括输入端口，并且在第一互连处的第一金属层中的开口包括输出端口。

公开(公告)号：US08566759B2

公开(公告)日：2013-10-22

申请号：US12046750

申请日：2008-03-12

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC分类号： G06F17/50

CPC分类号： G01R1/18 ,  G01R31/2851 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/00

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.

摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括：围绕和容纳布置在基板上的电路或电路装置的导电结构以及与导电结构相关联的至少一个馈电电容器和一个传输线，并将电源和信号提供给电路或电路装置 分别。 该设计结构还包括围绕设置在基板上的电路或电路装置的屏蔽结构以及布置在屏蔽结构侧的电容器或传输线的至少一个馈电。

公开(公告)号：US08514028B2

公开(公告)日：2013-08-20

申请号：US13211697

申请日：2011-08-17

申请人： Hanyi Ding ,  Pinping Sun ,  Hailing Wang

发明人： Hanyi Ding ,  Pinping Sun ,  Hailing Wang

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/04 ,  H03B5/1212 ,  H03B5/1243 ,  H03B2200/0034 ,  H04L25/0264

摘要： A voltage controlled oscillator (VCO), IC and CMOS IC including the VCO. The VCO includes an LC tank circuit, a pair of cross-coupled devices connected to the tank circuit and driving a pair of buffers. Each of the pair of cross-coupled devices includes a field effect transistor (FET) with an independently controllable body, e.g., the surface layer of a Silicon on Insulator (SOI) chip or the surface well of a multi-well chip. Diodes in the multi-well structure are biased off in each device. The tank circuit is coupled to the buffers solely through the FET drain to body capacitance.

摘要翻译： 压控振荡器（VCO），IC和CMOS IC包括VCO。 VCO包括LC槽电路，连接到储能电路的一对交叉耦合器件，并驱动一对缓冲器。 这对交叉耦合器件中的每一个包括具有可独立控制的体的场效应晶体管（FET），例如绝缘体上硅（SOI）芯片的表面层或多阱芯片的表面阱。 多孔结构中的二极管在每个器件中偏置。 储能电路仅通过FET漏极耦合到缓冲器到体电容。

公开(公告)号：US20130193584A1

公开(公告)日：2013-08-01

申请号：US13358792

申请日：2012-01-26

申请人： Hanyi Ding ,  Pinping Sun ,  Guoan Wang ,  Wayne H. Woods, JR.

发明人： Hanyi Ding ,  Pinping Sun ,  Guoan Wang ,  Wayne H. Woods, JR.

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

摘要： Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.

摘要翻译： 公开了具有功率分配器/组合器的芯片，包括芯片的模块和相关联的方法。 分隔器/组合器包括在衬底的相对侧上的第一和第二金属层。 互连件延伸穿过衬底并且包括：第一互连，围绕第一互连环形布置的第二互连和围绕第二互连环形布置的第三互连。 每个互连包括一个或多个内衬/填充有导体的通孔硅通孔。 对于功率分配器，第一互连处的第一金属层中的开口包括用于接收功率的输入端口，并且在第二互连处的第一或第二金属层中的开口包括用于向其它器件施加电力的输出端口。 对于功率组合器，在第二互连处的第一或第二金属层中的开口包括输入端口，并且在第一互连处的第一金属层中的开口包括输出端口。

公开(公告)号：US20130088403A1

公开(公告)日：2013-04-11

申请号：US13253260

申请日：2011-10-05

申请人： Pinping Sun ,  Hanyi Ding ,  Wayne H. Woods, JR.

发明人： Pinping Sun ,  Hanyi Ding ,  Wayne H. Woods, JR.

IPC分类号： H01Q1/50 ,  G06F17/50 ,  H01P1/22

CPC分类号： H01P1/22 ,  H03H7/07 ,  H03H7/24 ,  H03H11/245 ,  H03L5/00

摘要： A low phase variation attenuator uses a combined attenuation path and a phase network to significantly reduce a phase error between a reference signal and an attenuated signal without degrading the insertion loss. A grounded parallel connection of a resistor and a capacitor is employed in series with an attenuation transistor, which is connected to a middle of a two resistor voltage divider. The two resistor voltage divider includes two resistors of equal resistance that are connected in a series connection. The two resistor voltage divider is connected in a parallel connection with a reference transistor, which functions as a main switch for the transmission or attenuation of a radio frequency (RF) signal.

摘要翻译： 低相位变化衰减器使用组合的衰减路径和相位网络来显着地减小参考信号和衰减信号之间的相位误差而不降低插入损耗。 电阻和电容器的并联接地与衰减晶体管串联使用，该衰减晶体管连接到两个电阻分压器的中间。 两个电阻分压器包括两个串联连接的等电阻电阻。 两个电阻分压器与参考晶体管并联连接，参考晶体管用作发射或衰减射频（RF）信号的主开关。

公开(公告)号：US08415999B2

公开(公告)日：2013-04-09

申请号：US12845390

申请日：2010-07-28

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhenrong Jin ,  Francis F. Szenher

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhenrong Jin ,  Francis F. Szenher

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/22

摘要： A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.

公开(公告)号：US08405453B2

公开(公告)日：2013-03-26

申请号：US12839777

申请日：2010-07-20

申请人： Wayne H. Woods, Jr. ,  Guoan Wang ,  Hanyi Ding

发明人： Wayne H. Woods, Jr. ,  Guoan Wang ,  Hanyi Ding

IPC分类号： H03K5/00 ,  H01L27/24

CPC分类号： H01P1/127 ,  H01F17/0006 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L27/0629 ,  H01L28/10 ,  H01L2223/6627 ,  H01L2924/0002 ,  H03K17/145 ,  H01L2924/00

摘要： A semiconductor switching device includes a field effect transistor and an inductor structure that provides a frequency dependent inductance in a parallel connection. During the off-state of the semiconductor switching device, the frequency dependent impedance component due to the off-state parasitic capacitance of the switching device is cancelled by the frequency dependent inductance component of the inductor structure, which provides a non-linear impedance as a function of frequency. The inductor structure provides less inductance at a higher operating frequency than at a lower operating frequency to provide more effective cancellation of two impedance components of the parasitic capacitance and the inductance. Thus, the semiconductor switching device can provide low parasitic coupling at multiple operating frequencies. The operating frequencies of the semiconductor switching device can be at gigahertz ranges for millimeter wave applications.

摘要翻译： 半导体开关器件包括场效应晶体管和在并联连接中提供频率相关电感的电感器结构。 在半导体开关器件的截止状态期间，由开关器件的截止状态寄生电容引起的与频率相关的阻抗分量被电感器结构的频率相关的电感分量抵消，该电感器结构提供非线性阻抗作为 频率功能 电感器结构在较高工作频率下提供比在较低工作频率下更小的电感，以提供更有效地消除寄生电容和电感的两个阻抗分量。 因此，半导体开关器件可以在多个工作频率下提供低的寄生耦合。 对于毫米波应用，半导体开关器件的工作频率可以是千兆赫兹范围。

公开(公告)号：US08232920B2

公开(公告)日：2012-07-31

申请号：US12187442

申请日：2008-08-07

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

IPC分类号： H01Q1/38 ,  H01Q1/40

CPC分类号： H01Q1/2283 ,  H01Q1/40 ,  H01Q9/26 ,  H01Q9/285 ,  H01Q19/108 ,  H01Q19/30

摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

摘要翻译： 提供集成收发器，天线和接收器的半导体芯片。 收发器位于半导体衬底的前侧。 通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。 连接到收发器的天线位于位于基板正面的电介质层中。 反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。 可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。 还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。

公开(公告)号：US08193878B2

公开(公告)日：2012-06-05

申请号：US12144684

申请日：2008-06-24

申请人： Hanyi Ding ,  Wayne H. Woods, Jr.

发明人： Hanyi Ding ,  Wayne H. Woods, Jr.

IPC分类号： H01P1/18

CPC分类号： H01P9/00 ,  H01P1/184

摘要： A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.

摘要翻译： 一种用于提供具有固定特性阻抗的片上可变延迟传输线的设计结构，结构和方法。 制造传输线结构的方法包括形成传输线结构的信号线，形成在传输线结构中引起第一延迟和第一特性阻抗的第一接地返回结构，以及形成第二接地返回结构，其导致 传输线结构中的第二延迟和第二特性阻抗。 第一延迟与第二延迟不同，第一特征阻抗基本上与第二特征阻抗相同。

公开(公告)号：US08188808B2

公开(公告)日：2012-05-29

申请号：US12542958

申请日：2009-08-18

申请人： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne H. Woods, Jr.

发明人： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne H. Woods, Jr.

IPC分类号： H01P5/18 ,  H01P9/00

CPC分类号： H01P3/082 ,  H01L27/0617 ,  H01L27/0629 ,  H01P5/227

摘要： Branchline coupler structure using slow wave transmission line effect having both large inductance and large capacitance per unit length. The branchline coupler structure includes a plurality of quarter-wavelength transmission lines, at least one of which includes a high impedance arm and a low impedance arm. The high and low impedances are relative to each other. The high impedance arm includes a plurality of narrow cells and having an inductance of nL and a capacitance of C/n, and the low impedance arm includes a plurality of wide cells and having an inductance of L/n and capacitance of nC. The wide and narrow cells are relative to each other, and the wide and narrow cells are adjacent each other to form a signal layer having step discontinuous alternative widths.

摘要翻译： 使用慢波传输线效应的分支线耦合器结构具有每单位长度的大电感和大电容。 支线耦合器结构包括多个四分之一波长传输线，其中至少一个包括高阻抗臂和低阻抗臂。 高阻抗和低阻抗是相对的。 高阻抗臂包括多个窄电池并且具有nL的电感和C / n的电容，并且低阻抗臂包括多个宽电池并且具有L / n的电感和nC的电容。 宽和窄的单元彼此相对，并且宽和窄的单元彼此相邻以形成具有阶梯不连续替代宽度的信号层。