公开(公告)号：US09354891B2

公开(公告)日：2016-05-31

申请号：US13904660

申请日：2013-05-29

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F15/00 ,  G06F9/45 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F8/445 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30192 ,  G06F9/3822 ,  G06F9/3853

Abstract: A processor may include a vector functional unit that supports concurrent operations on multiple data elements of a maximum element size. The functional unit may also support concurrent execution of multiple distinct vector program instructions, where the multiple vector instructions each operate on multiple data elements of less than the maximum element size.

Abstract translation: 处理器可以包括支持对最大元素大小的多个数据元素的并行操作的向量功能单元。 功能单元还可以支持并行执行多个不同向量程序指令，其中多个向量指令各自对小于最大元素大小的多个数据元素进行操作。

公开(公告)号：US09348589B2

公开(公告)日：2016-05-24

申请号：US14218419

申请日：2014-03-18

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30192 ,  G06F9/345 ,  G06F9/3838

Abstract: Systems, apparatuses and methods for utilizing enhanced predicate registers which specify the element width and which elements are to be processed. The predicate size is dynamic, depending on the contents of the enhanced predicate register used for an instruction rather than being a static quality of a specific instruction. Specifying the element size in the enhanced predicate registers results in fewer instructions in an instruction set.

Abstract translation: 用于使用增强谓词寄存器的系统，装置和方法，其指定元素宽度和要处理的元素。 谓词大小是动态的，这取决于用于指令的增强谓词寄存器的内容，而不是特定指令的静态质量。 在增强谓词寄存器中指定元素大小导致指令集中的指令更少。

公开(公告)号：US09335980B2

公开(公告)日：2016-05-10

申请号：US13630328

申请日：2012-09-28

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/45 ,  G06F9/30

CPC classification number: G06F8/4441 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072

Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive a basis vector, an operand vector, a selection vector, and a control vector are disclosed. The executed instructions may also cause the processor to perform a wrapping propagate operation dependent upon the input vectors.

Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收基本向量，操作数向量，选择向量和控制向量的指令。 执行的指令还可以使得处理器根据输入向量来执行环绕传播操作。

公开(公告)号：US20160092217A1

公开(公告)日：2016-03-31

申请号：US14704396

申请日：2015-05-05

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Charles E. Tucker ,  Alexander C. Klaiber

IPC: G06F9/30

CPC classification number: G06F9/30021 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/325

Abstract: In an embodiment, a processor may implement a vector instruction set including one or more compare break instructions. The compare break instruction may take a pair of operands which may be compared to determine loop termination conditions, and may output a predicate vector indicating which vector elements correspond to loop iterations that are executed and which vector elements correspond to loop iterations that are not executed. The predicate vector may serve as a predicate to vector instructions forming the body of the loop, correctly executing the specified number of iterations. The compare break instruction may be coded to check for a variety of conditions (e.g. equal, not equal, greater than, less than, etc.). In an embodiment, the compare break instruction may take a predicate operand as well, which may be combined with the predicate vector produced by the comparison operations to produce the output vector.

Abstract translation: 在一个实施例中，处理器可以实现包括一个或多个比较中断指令的向量指令集。 比较中断指令可以采用一对可以与确定循环终止条件进行比较的操作数，并且可以输出指示哪些向量元素对应于执行的循环迭代的谓词向量，哪些向量元素对应于不执行的循环迭代。 谓词向量可以作为形成循环体的向量指令的谓词，正确执行指定数量的迭代。 比较中断指令可以被编码以检查各种条件（例如相等，不等于，大于，小于等）。 在一个实施例中，比较中断指令也可以采用谓词操作数，其可以与由比较操作产生的谓词向量组合以产生输出向量。

公开(公告)号：US09201608B2

公开(公告)日：2015-12-01

申请号：US14330320

申请日：2014-07-14

Applicant: Apple Inc.

Inventor： Ian C. Hendry ,  Rajabali Koduri ,  Jeffry E. Gonion

IPC: G06F12/08 ,  G06F3/06 ,  G06F1/32 ,  G06F12/02 ,  G06F12/06 ,  G06F17/30

CPC classification number: G06F3/0647 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0673 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/0646 ,  G06F12/08 ,  G06F17/30147 ,  G06F2003/0697 ,  Y02D10/14 ,  Y02D50/20

Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.

公开(公告)号：US20150089191A1

公开(公告)日：2015-03-26

申请号：US14034670

申请日：2013-09-24

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/3836

Abstract: In an embodiment, a processor includes an issue circuit configured to issue instruction operations for execution. The issue circuit may be configured to monitor the source operands of the instruction operations, and to issue instruction operations for which the source operands (including predicate operands, as appropriate) are resolved. Additionally, the issue circuit may be configured to detect a null predicate that indicates that none of the vector elements will be modified by a corresponding instruction operation. The issue circuit may be configured to issue the corresponding instruction operation with the null predicate even if other source operands are not yet resolved.

Abstract translation: 在一个实施例中，处理器包括配置成发出用于执行的指令操作的发行电路。 发布电路可以被配置为监视指令操作的源操作数，并且发出解决源操作数（包括适当的谓词操作数）的指令操作。 此外，发行电路可以被配置为检测指示不会通过相应的指令操作来修改向量元素的零谓词。 即使其他源操作数尚未解决，发布电路也可以被配置为使用空谓词发出相应的指令操作。

公开(公告)号：US20150089189A1

公开(公告)日：2015-03-26

申请号：US14034629

申请日：2013-09-24

Applicant: APPLE INC.

Inventor： Jeffry E. Gonion

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F8/452 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30076 ,  G06F9/3838

Abstract: In an embodiment, a processor may implement a vector instruction set including predicate vectors and multiple vector element sizes. The vector instruction set may include predicate vector pack and unpack instructions. Responsive to the predicate vector pack instruction, the processor may pack predicates from multiple predicate vector source registers into a destination predicate vector register. Responsive to the predicate vector unpack instruction, the processor may select a portion of a source predicate vector register and write the result to a destination predicate vector register. Additionally, the predicate vector register may store one or more vector attributes associated with the corresponding vector. The processor may modify the attribute as part of the pack/unpack operation (e.g. based on a pack/unpack factor). Additionally, vector pack/unpack instructions that are controlled by the attribute in a corresponding predicate vector register may be implemented.

Abstract translation: 在一个实施例中，处理器可以实现包括谓词向量和多个向量元素大小的向量指令集。 矢量指令集可以包括谓词向量包和解包指令。 响应于谓词向量包指令，处理器可以将来自多个谓词向量源寄存器的谓词打包到目标谓词向量寄存器中。 响应于谓词向量解包指令，处理器可以选择源谓词向量寄存器的一部分，并将结果写入目的地谓词向量寄存器。 另外，谓词向量寄存器可以存储与相应向量相关联的一个或多个向量属性。 处理器可以将该属性修改为打包/解包操作的一部分（例如，基于打包/打包因子）。 此外，可以实现由对应的谓词向量寄存器中的属性控制的向量包/解包指令。

公开(公告)号：US08555037B2

公开(公告)日：2013-10-08

申请号：US13625164

申请日：2012-09-24

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/302

CPC classification number: G06F9/30014 ,  G06F8/4441 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/3838 ,  G06F9/3842

Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a minima or maxima operation on another input vector dependent upon the input vector and the control vector.

Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使得处理器根据输入向量和控制向量对另一个输入向量执行最小或最大值操作。

公开(公告)号：US08539205B2

公开(公告)日：2013-09-17

申请号：US13625131

申请日：2012-09-24

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F9/302

CPC classification number: G06F8/4441 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30072 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a product or quotient operation on another input vector dependent upon the input vector and the control vector.

Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使得处理器根据输入向量和控制向量对另一输入向量执行乘积或商运算。

公开(公告)号：US20130024656A1

公开(公告)日：2013-01-24

申请号：US13628857

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion

IPC: G06F15/78

CPC classification number: G06F8/4441 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30072

Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a Boolean operation on another input vector dependent upon the input vector and the control vector.

Abstract translation: 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使得处理器根据输入向量和控制向量对另一输入向量执行布尔运算。