公开(公告)号：US20080137411A1

公开(公告)日：2008-06-12

申请号：US12021761

申请日：2008-01-29

Applicant: Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

Inventor： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC: G11C16/26

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

公开(公告)号：US20070133295A1

公开(公告)日：2007-06-14

申请号：US11295776

申请日：2005-12-06

Applicant: Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

Inventor： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC: G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

Abstract translation: 公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。 一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。 例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。 因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

公开(公告)号：US20070091685A1

公开(公告)日：2007-04-26

申请号：US11550502

申请日：2006-10-18

Applicant: Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

Inventor： Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC: G11C11/34

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5624

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract translation: 通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。 通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。 精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

公开(公告)号：US20070058436A1

公开(公告)日：2007-03-15

申请号：US11550499

申请日：2006-10-18

Applicant: Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

Inventor： Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC: G11C11/34

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5624

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract translation: 通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。 通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。 精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

公开(公告)号：US07088621B2

公开(公告)日：2006-08-08

申请号：US11207427

申请日：2005-08-18

Applicant: Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

Inventor： Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3454 ,  G11C16/3459

Abstract: In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.

公开(公告)号：US20060163645A1

公开(公告)日：2006-07-27

申请号：US11278778

申请日：2006-04-05

Applicant: Daniel Guterman ,  Gheorghe Samachisa ,  Yupin Fong ,  Eliyahou Harari

Inventor： Daniel Guterman ,  Gheorghe Samachisa ,  Yupin Fong ,  Eliyahou Harari

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  G11C16/0458 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7881

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.

Abstract translation: 新型存储单元利用源侧注入，允许非常小的编程电流。 如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。 在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。 在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。 在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于 后续写操作。 在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。 如果所有待编程的单元都已被正确编程，则位线电流将基本为零。 如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。 重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

公开(公告)号：US20060140011A1

公开(公告)日：2006-06-29

申请号：US11021872

申请日：2004-12-23

Applicant: Yupin Fong ,  Daniel Guterman

Inventor： Yupin Fong ,  Daniel Guterman

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/16

Abstract: For a non-volatile memory system, compressing the erase threshold voltage distribution into the lowest threshold voltage state will decrease the valid data threshold voltage window. Decreasing the valid data threshold voltage window reduces the floating gate to floating gate coupling effect. The compression can be performed as part of the erase process or part of the programming operation.

Abstract translation: 对于非易失性存储器系统，将擦除阈值电压分布压缩到最低阈值电压状态将降低有效数据阈值电压窗口。 降低有效的数据阈值电压窗口可以将浮栅减少到浮栅耦合效应。 压缩可以作为擦除过程的一部分或编程操作的一部分来执行。

公开(公告)号：US20050162924A1

公开(公告)日：2005-07-28

申请号：US10766786

申请日：2004-01-27

Applicant: Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

Inventor： Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC: A43B13/18 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C27/00 ,  G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3481 ,  G11C27/005

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract translation: 通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。 通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。 精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

公开(公告)号：US06894930B2

公开(公告)日：2005-05-17

申请号：US10175764

申请日：2002-06-19

Applicant: Henry Chien ,  Yupin Fong

Inventor： Henry Chien ,  Yupin Fong

IPC: G11C16/04 ,  G11C11/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00

CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

Abstract: A NAND flash memory structure and method of making a flash memory structure with a wordline that provides shielding from Yupin effect errors and from disturbs.

Abstract translation: 一种NAND闪速存储器结构和方法，其制造具有字幕线的闪存结构，其提供对Yupin的屏蔽效应误差和来自干扰。

公开(公告)号：US20050047223A1

公开(公告)日：2005-03-03

申请号：US10966451

申请日：2004-10-15

Applicant: Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker Quader

Inventor： Jian Chen ,  Tomoharu Tanaka ,  Yupin Fong ,  Khandker Quader

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/00 ,  G11C16/04 ,  G11C16/12 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: G11C11/5628 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

Abstract: A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.