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公开(公告)号：US20240363187A1
公开(公告)日：2024-10-31
申请号：US18635569
申请日：2024-04-15
Applicant: STMicroelectronics International N.V.
Inventor： Praveen Kumar VERMA , Christophe LECOCQ , Yagnesh Dineshbhai VADERIYA , Anuj DHILLON , Cedric ESCALLIER , Harsh RAWAT , Kedar Janardan DHORI
CPC classification number: G11C29/46 , G11C29/022 , G11C29/32 , G11C2029/3202
Abstract: A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.
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公开(公告)号：US20240361791A1
公开(公告)日：2024-10-31
申请号：US18139786
申请日：2023-04-26
Applicant: STMicroelectronics International N.V.
Inventor： Federico MUSARRA , Sandor PETENYI
Abstract: An electronic device includes multiple integrated circuits, each containing a power transistor connected between an input voltage node and a load node, as well as a regulation circuit generating at least one sense current representing the output current of the power transistor. The regulation circuits modulate the output currents of their power transistors based on a value derived from the sense currents generated by the regulation circuits of other integrated circuits. This derived value can be based on an average of the sense currents generated by the regulation circuits or on one of the sense currents. In particular, the integrated circuits can be arranged in a daisy-chained relationship, allowing each regulation circuit to compare its sense current with the one from the immediately preceding circuit, except for the first regulation circuit, which compares its sense current with the last circuit's sense current in the chain.
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公开(公告)号：US20240356784A1
公开(公告)日：2024-10-24
申请号：US18639419
申请日：2024-04-18
Applicant: STMicroelectronics International N.V.
Inventor： Nicolas Moeneclaey , Gilles Troussel , Christophe Tourniol
CPC classification number: H04L25/026 , H04L12/40013 , H04L25/0272 , H04L25/0292 , H04L2012/40215
Abstract: The present disclosure relates to device including first and second terminals connected to a bus, third and fourth terminals connected to power supply and reference potentials. A first transistor and a first resistor are in series between the first terminal and a first diode connected to the third terminal. A second resistor, a second transistor and a second diode are in series between the first and fourth terminals. A third transistor and a third resistor are in series between the first diode and the second terminal. A fourth resistor, a fourth transistor and a third diode are in series between the second and fourth terminals. At each consecutive transmission of a dominant bit and of a recessive bit, a circuit sets the transistors at the ON state during a time period starting with the recessive bit.
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94.发明公开公开(公告)号：US20240356537A1
公开(公告)日：2024-10-24
申请号：US18631798
申请日：2024-04-10
Applicant: STMicroelectronics International N.V.
Inventor： Massimo Pozzoni , Paolo Viola , Pasquale D'Argenio , Augusto Andrea Rossi
IPC: H03K3/017 , H03K5/24 , H03K17/567
CPC classification number: H03K3/017 , H03K5/24 , H03K17/567
Abstract: In embodiments, a clock signal calibration circuit for communication transmitters includes a multiplexer that creates a combined output pattern from input data patterns in reaction to the clock signal's edges. It uses a calibration data pattern generator, which supplies two sequential patterns—the second being a shifted copy of the first—to the multiplexer. An averaging circuit then generates two averaged signals corresponding to these patterns. Duty cycle control circuitry corrects clock signal imbalances if these averaged signals are unequal, thus adjusting the duty cycle distortion to achieve an ideal 50% duty cycle.
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公开(公告)号：US20240354742A1
公开(公告)日：2024-10-24
申请号：US18632120
申请日：2024-04-10
Applicant: STMicroelectronics International N.V.
Inventor： Philippe ALARY
CPC classification number: G06Q20/3552 , G06Q20/352 , G06V40/13
Abstract: A device facilitates personalizing an integrated circuit card including a fingerprint sensor. The device includes a support sheet, a first antenna located on top of and in contact with a surface of the support sheet, and at least one second antenna located on top of and in contact with the surface of the support sheet. The at least one second antenna is connected to the first antenna.
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Patent Agency Ranking
公开(公告)号：US20240348188A1
公开(公告)日：2024-10-17
申请号：US18622199
申请日：2024-03-29
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Laurent GONTHIER , Minjie LI
Abstract: The present disclosure relates to a control circuit of a triac or thyristor having its driving reference terminal connected to a first reference node and coupled to a voltage rectifier comprising at least a semiconductor device connected between the first reference node and a second reference node of the control circuit comprising: a first bipolar transistor; and a driving circuit of the first transistor referenced to the second reference node.
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公开(公告)号：US20240345229A1
公开(公告)日：2024-10-17
申请号：US18133299
申请日：2023-04-11
Applicant: STMicroelectronics International N.V.
Inventor： Colin CAMPBELL , Marco ANTONELLI , Calum RITCHIE , Bhagya Prakash BANDUSENA
IPC: G01S7/4865 , G01S17/10 , H01L31/0203 , H01L31/0216 , H01L31/173
CPC classification number: G01S7/4865 , G01S17/10 , H01L31/0203 , H01L31/02162 , H01L31/173
Abstract: A device includes an optical integrated circuit device mounted over an upper surface of a support substrate. The optical integrated circuit device includes an optical sensor array supported by a semiconductor substrate made of a first semiconductor material. A discrete semiconductor block, made of a second semiconductor material, is mounted over an upper surface of the optical integrated circuit device adjacent the optical sensor array. The first and second semiconductor materials have substantially matched coefficients of thermal expansion. A parallelpipedal-shaped optical filter is mounted over an upper surface of the discrete semiconductor block and extends over the optical sensor array. One or more edges/corners of the parallelpipedal-shaped optical filter cantilever over the optical sensor array without any provided support.
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公开(公告)号：US20240333430A1
公开(公告)日：2024-10-03
申请号：US18601352
申请日：2024-03-11
Applicant: STMicroelectronics International N.V.
Inventor： Roland Van Der Tuijn
IPC: H04L1/1607 , H04L5/00
CPC classification number: H04L1/1657 , H04L5/0055
Abstract: A method of controlling a receiver of radio frequency communications includes intervals between the reception of a data packet header and an acknowledgement sent by the receiver being constant, and, once a packet has been correctly received, circuits of the receiver are put into standby for a duration corresponding to the interval after each reception of a header of same rank as that of the correctly received packet.
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公开(公告)号：US20240333318A1
公开(公告)日：2024-10-03
申请号：US18612222
申请日：2024-03-21
Applicant: STMicroelectronics International N.V.
Inventor： Nunzio Spina , Giuseppe Palmisano
IPC: H04B1/00
CPC classification number: H04B1/006 , H04B1/0078
Abstract: A circuit for transmitting/receiving signals through a galvanic isolation comprises an antenna transmitting/receiving radiofrequency signals modulated over a radiofrequency carrier, a transmitter receiving an input data signal, and a receiver delivering an output data signal. First and second capacitive circuitry are arranged between the antenna and the receiver and the transmitter, respectively. First and second switching circuitry couple the first and second capacitive circuitry to the antenna in an inductive-capacitive network, alternately: in a transmission mode, the first switching circuitry couples the first capacitive circuitry to ground with the receiver disabled, and the second switching circuitry decouples the second capacitive circuitry from the inductive-capacitive network with the transmitter enabled, and in a reception mode, the first switching circuitry decouples the first capacitive circuitry from ground, with the receiver enabled, and the second switching circuitry couples the second capacitive circuitry to the inductive-capacitive network with the transmitter disabled.
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公开(公告)号：US20240333302A1
公开(公告)日：2024-10-03
申请号：US18127848
申请日：2023-03-29
Inventor： Francesco STILGENBAUER , Edoardo BOTTI , Piero MALCOVATI , Paolo Stefano CROVETTI , Edoardo BONIZZONI , Matteo DE FERRARI
IPC: H03M3/00
Abstract: A delta-sigma modulator includes a loop filter circuit having a first input that receives an input signal and a second input that receives a feedback signal. The loop filter circuit generates a filtered signal. A quantizer circuit quantizes the integrated signal to generate an output signal. An anti-windup circuit detects instances where the integrated signal is outside an input signal input of the quantizer circuit and in response thereto generates a dead zone signal having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range. The feedback signal is a sum of the output signal and the dead zone signal.
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