PACKAGE STRUCTURE
    91.
    发明公开
    PACKAGE STRUCTURE 审中-公开

    公开(公告)号:US20240080984A1

    公开(公告)日:2024-03-07

    申请号:US18149660

    申请日:2023-01-03

    CPC classification number: H05K1/181 H01L23/5385 H01L25/0655 H01L24/16

    Abstract: A package structure, including a circuit board, multiple circuit structure layers, at least one bridge structure, and at least one supporting structure, is provided. The circuit structure layer is disposed on the circuit board. The bridge structure is connected between the two adjacent circuit structure layers. The supporting structure is located between the two adjacent circuit structure layers, and the supporting structure has a first end and a second end opposite to each other and respectively connecting the bridge structure and the circuit board.

    METHOD OF ANOMALY DETECTION, METHOD OF BUILDING UPSTREAM-AND-DOWNSTREAM CONFIGURATION, AND MANAGEMENT SYSTEM OF SENSORS

    公开(公告)号:US20240027416A1

    公开(公告)日:2024-01-25

    申请号:US17969641

    申请日:2022-10-19

    CPC classification number: G01N33/0075 G01N33/18

    Abstract: A method of building upstream-and-downstream configuration of sensors includes determining two sets of geographic position data of a target sensor and a candidate sensor, obtaining pollution-associated periods according to pieces of flow field data, the sets of geographic position data and pieces of target sensing data of the target sensor to determine a pollution-associated period, calculating a correlation between target sensing data obtained by the target sensor during the pollution-associated period and candidate sensing data obtained by the candidate sensor during the associated air pollution period to obtain sensor correlations, and determining the target sensor and the candidate sensor having a upstream-and-downstream relationship with the candidate sensor being used as a satellite sensor of the target sensor when a quantity ratio of sensor correlations being larger than or equal to a correlation threshold is larger than or equal to a default ratio.

    ELECTRONIC DEVICE AND METHOD FOR ACCELERATING CANONICAL POLYADIC DECOMPOSITION

    公开(公告)号:US20240012873A1

    公开(公告)日:2024-01-11

    申请号:US18077126

    申请日:2022-12-07

    CPC classification number: G06F17/16 G06F17/145 G06F17/147

    Abstract: An electronic device and a method for accelerating canonical polyadic (CP) decomposition are provided. The method includes: performing at least one of a Walsh-Hadamard transform (WHT) operation and a discrete cosine transform (DCT) operation on a first factor matrix, a second factor matrix, and a tensor respectively to update the first factor matrix, the second factor matrix and the tensor; sampling the updated first factor matrix and the updated second factor matrix to generate a first sampled matrix, and sampling an unfolded matrix of the updated tensor to generate a second sampled matrix; solving a least square problem of the first sampled matrix and the second sampled matrix to generate or update a third factor matrix of the tensor so as to update multiple components of the tensor; and outputting multiple components after an updating of multiple components is finished.

    Method for manufacturing display array

    公开(公告)号:US11855062B2

    公开(公告)日:2023-12-26

    申请号:US17974531

    申请日:2022-10-27

    CPC classification number: H01L25/18 H01L27/1259 H01L27/156

    Abstract: A method for manufacturing a display array includes the following steps: providing a substrate and forming a semiconductor stacked layer on the substrate; forming an insulating layer and a plurality of electrode pads on an outer surface of the semiconductor stacked layer, the insulating layer and the electrode pads directly contacting the semiconductor stacked layer, wherein the insulating layer has a plurality of openings spaced apart from each other; and transferring the semiconductor stacked layer, the insulating layer and the electrode pads from the substrate to a driving backplane, wherein the electrode pads are respectively electrically connected to the driving backplane through the openings of the insulating layer to form a plurality of light emitting regions in the semiconductor stacked layer as the electrode pads and the semiconductor stacked layer are energized by the driving backplane.

    In-plane magnetized spin-orbit magnetic device

    公开(公告)号:US11844288B2

    公开(公告)日:2023-12-12

    申请号:US17168146

    申请日:2021-02-04

    CPC classification number: H10N52/80 H10N50/85 H10N52/00 H10B61/00

    Abstract: An in-plane magnetized spin-orbit magnetic device is provided. The in-plane magnetized spin-orbit magnetic device includes a heavy metal layer, an upper electrode and a magnetic tunnel junction. The magnetic tunnel junction is disposed between the heavy metal layer and the upper electrode. The magnetic tunnel junction includes a free layer and a pinned layer. The free layer is disposed on the heavy metal layer, and the free layer has a first film plane area. The pinned layer is disposed on the free layer, and the pinned layer has a second film plane area. There is a preset angle between a long axis direction of a film plane shape of the free layer and a long axis direction of a film plane shape of the pinned layer, and the first film plane area is larger than the second film plane area.

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