公开(公告)号：US20250072097A1

公开(公告)日：2025-02-27

申请号：US18940439

申请日：2024-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chuan-Hui LU ,  Ming-Feng SHIEH ,  Ming-Jhih KUO ,  Ming-Wen HSIAO

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/308

Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, a groove pattern is formed in the hard mask layer, one or more first resist layers are formed over the hard mask layer having the groove pattern, a first photo resist pattern is formed over the one or more first resist layers, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer with the groove pattern are patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.

公开(公告)号：US20250072096A1

公开(公告)日：2025-02-27

申请号：US18606375

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Woong SHIM ,  Seong Heum CHOI ,  Do Sun LEE ,  Hyo Seok CHOI ,  Rak Hwan KIM ,  Chung Hwan SHIN

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of fabricating a semiconductor device includes: forming an active pattern on a substrate, forming a source/drain pattern on the active pattern, forming a contact hole on the source/drain pattern, forming a contact barrier layer, which has an upper surface of a first height based on a bottom surface of the contact hole, in the contact hole, forming a passivation layer on the contact barrier layer in the contact hole, forming a mask layer on the passivation layer in the contact hole, removing an upper portion of the contact barrier layer so that an upper surface of the contact barrier layer has a second height lower than the first height, removing the passivation layer and the mask layer, and forming a contact filling layer, which covers the upper surface of the contact barrier layer and fills the contact hole, in the contact hole.

公开(公告)号：US20250072070A1

公开(公告)日：2025-02-27

申请号：US18507039

申请日：2023-11-11

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Chen An Hsu ,  Chien-Wei Lee ,  Anhao Cheng ,  Yen-Liang Lin ,  Ru-Shang Hsiao ,  Wei-Lun Chung

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate and a first epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a first doped region located in the semiconductor layer below the first epitaxial source/drain feature. The first doped region includes a dopant at a first concentration. The semiconductor structure includes a second epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a second doped region located in the semiconductor layer below the second epitaxial source/drain feature. The second doped region includes the dopant at a second concentration that is less than the first concentration.

公开(公告)号：US20250069893A1

公开(公告)日：2025-02-27

申请号：US18938789

申请日：2024-11-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsu Ming HSIAO ,  Shen WANG ,  Kung Shu HSU

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234

Abstract: Recesses may be formed in portions of an ILD layer of a semiconductor device in a highly uniform manner. Uniformity in depths of the recesses may be increased by configuring flows of gases in an etch tool to promote uniformity of etch rates (and thus, etch depth) across the semiconductor device, from semiconductor device to semiconductor device, and/or from wafer to wafer. In particular, the flow rates of gases at various inlets of the tch tool may be optimized to provide recess depth tuning, which increases the process window for forming the recesses in the portions of the ILD layer. In this way, the increased uniformity of the recesses in the portions of the ILD layer enables highly uniform capping layers to be formed in the recesses.

公开(公告)号：US12237393B2

公开(公告)日：2025-02-25

申请号：US17853955

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Ting Ko ,  Bi-Fen Wu ,  Chi-On Chui

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

公开(公告)号：US12237372B2

公开(公告)日：2025-02-25

申请号：US18295246

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Jia-Ni Yu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Mao-Lin Huang

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

公开(公告)号：US12237367B2

公开(公告)日：2025-02-25

申请号：US17593034

申请日：2021-04-12

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Junchao Zhang ,  Cheng Yeh Hsu

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/8234

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate, the surface of the semiconductor substrate having a plurality of active areas and shallow trench isolation areas arranged in a first direction; etching the active areas and the shallow trench isolation areas in a direction perpendicular to the first direction to form first recesses and second recesses; covering the surfaces of the first recesses and the second recesses with an adhesive layer and a metal layer; and secondarily etching the metal layer and the adhesive layer in the direction perpendicular to the first direction to form a contact hole, the depth of the adhesive layer in the contact hole being defined as H2.

公开(公告)号：US12237321B2

公开(公告)日：2025-02-25

申请号：US17843770

申请日：2022-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shun Li Chen ,  Fei Fan Duan ,  Ting Yu Chen

IPC: H01L27/02 ,  H01L21/8234 ,  H01L27/118

Abstract: A filler cell region (in a semiconductor device) includes: gate segments, a majority of first ends of which substantially align with a first reference line that parallel and proximal to a top boundary of the filler cell region, and a majority of second ends of which substantially align with a second reference line that is parallel and proximal to a bottom boundary of the filler cell region. First and second gate segments extend continuously across the filler cell region; and third & fourth and fifth & sixth gate segments are correspondingly coaxial and separated by corresponding gate-gaps. Relative to the first direction: a first end of the first gate segment extends to the top boundary of the filler cell region; and a second end of the second gate segment extends to the bottom boundary of the filler cell region.

公开(公告)号：US12237228B2

公开(公告)日：2025-02-25

申请号：US18345148

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Hung-Chi Wu ,  Chia-Ching Lee ,  Pin-Hsuan Yeh ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/02 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

公开(公告)号：US20250063809A1

公开(公告)日：2025-02-20

申请号：US18940119

申请日：2024-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wang-Chun Huang ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure describes a structure including a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate and a method of forming the structure. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.