公开(公告)号：US20240405882A1

公开(公告)日：2024-12-05

申请号：US18205748

申请日：2023-06-05

Applicant: XILINX, INC.

Inventor： Adebabay M. BEKELE ,  Mayank RAJ ,  Chuan XIE ,  Sandeep KUMAR ,  Zhaowen WANG ,  Sukruth PATTANAGIRI GIRIYAPPA ,  Parag UPADHYAYA ,  Yohan FRANS

IPC: H04B10/54

Abstract: Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a data pattern to an optical modulator device. The method also includes identifying, for each heater control value of a plurality of heater control values for a heater thermally coupled with the optical modulator device, an optical modulation amplitude corresponding to the heater control value based on a corresponding photodiode current value identified while transmitting the data pattern. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based on a plurality of optical modulation amplitudes corresponding to the plurality of heater control values according to the identifying. The method also includes controlling the heater based at least in part on the determined maximum optical modulation amplitude that has been modified according to scaling maximum photodiode current values.

公开(公告)号：US20220415788A1

公开(公告)日：2022-12-29

申请号：US17357087

申请日：2021-06-24

Applicant: XILINX, INC.

Inventor： Zhaoyin Daniel WU ,  Parag UPADHYAYA ,  Hong SHI

IPC: H01L23/522 ,  H01Q1/22

Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

公开(公告)号：US20220407676A1

公开(公告)日：2022-12-22

申请号：US17351028

申请日：2021-06-17

Applicant: XILINX, INC.

Inventor： Wenfeng ZHANG ,  Zhaoyin Daniel WU ,  Parag UPADHYAYA

IPC: H04L7/00 ,  H04B1/16

Abstract: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.

公开(公告)号：US20210288590A1

公开(公告)日：2021-09-16

申请号：US16814626

申请日：2020-03-10

Applicant: XILINX, INC.

Inventor： Junho CHO ,  Kevin ZHENG ,  Parag UPADHYAYA

IPC: H02M7/483

Abstract: An example continuous time linear equalizer (CTLE) includes a first inverter; a second inverter having an input to receive an input signal; a capacitor coupled between an input of the first inverter and the input of the second inverter; a resistor coupled between a common-mode voltage and the input of the first inverter; a third inverter having an output to provide an output signal; and a node comprising an output of the first inverter, an output of the second inverter, an input of the third inverter, and the output of the third inverter.

公开(公告)号：US20240369864A1

公开(公告)日：2024-11-07

申请号：US18143846

申请日：2023-05-05

Applicant: XILINX, INC.

Inventor： Chuan XIE ,  Mayank RAJ ,  Anish JOSHI ,  Zakriya MOHAMMED ,  Gareeyasee SAHA ,  Parag UPADHYAYA ,  Yohan FRANS

IPC: G02F1/025 ,  G02F1/01

Abstract: A silicon-on-insulator (SOI) dense-wavelength-division-multiplexing (DWDM) device includes micro-ring modulators (MRMs) having radii under 5 micrometers. A 16-channel embodiment may provide a free spectral range of 3.2 THz, 200 GHz channel spacing, 41 GHz bandwidth, and a Q factor of 4500. PN junctions of rib ring waveguides (RWRs) may be perpendicular or parallel with a plane of the RWRs. On-chip inductive components may be used to match reactances of the PN junctions. The RWRs may be relatively wide and a rib bus waveguide may be relatively narrow (e.g., narrower than the RWRs). MRM outer slaps may be wider than inner slabs. Regions inside and outside of the RWRs, including slabs at optical coupling gaps may be doped to improve modulation efficiency. Regions of the rib bus waveguide distant from the optical coupling gaps may be undoped. Cavities may be provided below the MRMs and associated heater elements.

公开(公告)号：US20230050659A1

公开(公告)日：2023-02-16

申请号：US17398675

申请日：2021-08-10

Applicant: XILINX, INC.

Inventor： Wenfeng ZHANG ,  Parag UPADHYAYA

IPC: H03K5/003 ,  H04B1/16 ,  H04L27/32 ,  H03K3/037

Abstract: Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.

公开(公告)号：US20240396638A1

公开(公告)日：2024-11-28

申请号：US18202512

申请日：2023-05-26

Applicant: XILINX, INC.

Inventor： Adebabay M. BEKELE ,  Mayank RAJ ,  Chuan XIE ,  Sandeep KUMAR ,  Zhaowen WANG ,  Sukruth PATTANAGIRI GIRIYAPPA ,  Parag UPADHYAYA ,  Yohan FRANS

IPC: H04B10/54 ,  H04B10/50 ,  H04B10/508

Abstract: Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a first data pattern to an optical modulator device. The method also includes determining, while transmitting the first data pattern and for each heater control value of a plurality of heater control values for a heater, a photodiode current value associated with the optical modulator device to generate a plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based at least in part on the plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes controlling the heater for the optical modulator device based on the maximum optical modulation amplitude.

公开(公告)号：US20230188314A1

公开(公告)日：2023-06-15

申请号：US17644066

申请日：2021-12-13

Applicant: XILINX, INC.

Inventor： Shaojun MA ,  Chi Fung POON ,  Kevin ZHENG ,  Parag UPADHYAYA

IPC: H04L7/00 ,  H03K19/21

CPC classification number: H04L7/0037 ,  H03K19/21

Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

公开(公告)号：US20220102293A1

公开(公告)日：2022-03-31

申请号：US17037363

申请日：2020-09-29

Applicant: XILINX, INC.

Inventor： Chi Fung POON ,  Asma LARABA ,  Parag UPADHYAYA

IPC: H01L23/66 ,  H01L25/16 ,  H01L23/538

Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.