公开(公告)号：US20230198530A1

公开(公告)日：2023-06-22

申请号：US17555212

申请日：2021-12-17

Applicant: XILINX, INC.

Inventor： Shaojun MA ,  Chi Fung POON

IPC: H03L7/099 ,  H03K17/687 ,  G06F1/06

CPC classification number: H03L7/0995 ,  G06F1/06 ,  H03K17/6872 ,  H03K17/6874

Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.

公开(公告)号：US20230188314A1

公开(公告)日：2023-06-15

申请号：US17644066

申请日：2021-12-13

Applicant: XILINX, INC.

Inventor： Shaojun MA ,  Chi Fung POON ,  Kevin ZHENG ,  Parag UPADHYAYA

IPC: H04L7/00 ,  H03K19/21

CPC classification number: H04L7/0037 ,  H03K19/21

Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

公开(公告)号：US20210152180A1

公开(公告)日：2021-05-20

申请号：US16688130

申请日：2019-11-19

Applicant: Xilinx, Inc.

Inventor： Jaewook Shin ,  Parag Upadhyaya ,  Shaojun MA

IPC: H03L7/24 ,  H03K3/03 ,  H03L7/099 ,  H03L7/083 ,  H03B5/12 ,  H04L7/033 ,  G06F1/08

Abstract: A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.