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公开(公告)号：US12057083B2
公开(公告)日：2024-08-06
申请号：US17292507
申请日：2021-04-29
Inventor： Xiaochen Li , Gui Chen , Qiang Gong
IPC: G09G3/36
CPC classification number: G09G3/3655 , G09G2300/0426 , G09G2310/08 , G09G2320/0214
Abstract: A display device is disclosed. The display device includes a control module and a display panel connected to the control module. Wherein, the display panel includes a plurality of pixel electrodes; a plurality of first common electrodes disposed opposite to the pixel electrodes and connected to the control module by common connecting lines; and a liquid crystal layer disposed between the first common electrodes and the pixel electrodes. Wherein, the control module is configured to allow a constant electrical potential difference to exist between the first common electrodes and the pixel electrodes.
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公开(公告)号：US10262613B2
公开(公告)日：2019-04-16
申请号：US15324057
申请日：2016-08-26
Inventor： Qiang Gong , Gui Chen , Chao Wang
IPC: G09G3/36 , G02F1/1345 , G02F1/1362
Abstract: The present disclosure provides a gate driver on array (GOA) circuit. A low level signal source is used to output a low level signal, a first high level signal source is used to output a first high level signal, and the second high level signal source is used to output the second high level signal. A cascade signal latch module is used to latch a cascade signal of a current grade. A gate driving signal generating module generates a preparation gate driving signal of the current grade. A gate driving signal outputting module is used to output a gate driving signal of the current grade.
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公开(公告)号：US10043912B2
公开(公告)日：2018-08-07
申请号：US15201439
申请日：2016-07-02
Inventor： Gui Chen , Qiang Gong
IPC: H01L27/14 , H01L29/786 , H01L27/12 , G02F1/1333 , G02F1/1343 , G06F3/041 , G06F3/044
Abstract: The present disclosure relates to an array substrate and the manufacturing method thereof. The array substrate includes a glass substrate. The shading metal layer and the buffering layer are formed on the glass substrate in sequence. The TFT layer is formed on the buffering layer, and the TFT is arranged above the shading metal layer. The insulation layer and the organic layer are formed on the TFT layer in sequence. In addition, the pixel electrode layer connects to the source/drain of the TFT via the first through hole. The touch electrode layer connects to the shading metal layer via the second through hole. The passivation layer is configured between the pixel electrode layer and the touch electrode layer. In this way, the manufacturing process is simplified, and the coupling capacitance between the touch electrode and the signal line may be effectively reduced.
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公开(公告)号：US09628050B2
公开(公告)日：2017-04-18
申请号：US14783100
申请日：2015-08-10
Inventor： Mang Zhao , Yong Tian , Gui Chen , Caiqin Chen , Xin Zhang
CPC classification number: H03K3/012 , G09G3/3677 , G09G2300/0408 , G09G2300/0814 , G09G2310/0202 , G09G2310/0289
Abstract: A scan driving circuit configured for driving cascaded scan lines is provided, which includes an input control module, a latch module, a driving-signal generation module, an output control module, a constant high voltage source and a constant low voltage source. The scan driving circuit of the present invention drives the input control module through cascade signals of a preceding stage and cascade signals of a succeeding stage, so as to reduce interference and the driving power consumption of the scan driving circuit.
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公开(公告)号：US10579176B2
公开(公告)日：2020-03-03
申请号：US15841332
申请日：2017-12-14
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Shihpo Chou , Gui Chen , Jingfeng Xue
IPC: G06F3/041 , G06F3/044 , G02F1/1333 , G02F1/1343 , G02F1/1362
Abstract: A self-capacitive touch panel structure includes a touch detection chip and multiple self-capacitance electrodes arranged as a matrix and isolated with each other. Each self-capacitance electrode connected with the touch detection chip through a connection line. Each self-capacitance electrode electrically connected with a corresponding connection line through at least one via hole. A group of connection lines connected with a same column of the multiple self-capacitance electrodes are divided into an odd number group and an even number group. The connection lines in the odd number group are sequentially connected with a terminal of a corresponding self-capacitance electrode of the same column of the self-capacitance electrodes. The connection lines in the even number group are sequentially connected with a terminal of a corresponding self-capacitance electrode of the same column of the self-capacitance electrodes. An in-cell touch panel and a liquid crystal display including above structure are also disclosed.
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Patent Agency Ranking
公开(公告)号：US10235957B2
公开(公告)日：2019-03-19
申请号：US15321389
申请日：2016-10-12
Inventor： Qiang Gong , Gui Chen , Guanghui Hong
IPC: G09G3/36
Abstract: A gate driver on array circuit includes a first driver module and a second driver module. The first driver module includes a first driver unit, a first output unit, and a first reset unit. The second driver module includes a second driver unit, a second output unit, and a second reset unit. The first output unit is used for generating a present stage scan drive signal and a present stage cascade signal. The second output unit is used for generating the present stage scan drive signal and the present stage cascade signal.
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公开(公告)号：US09935127B2
公开(公告)日：2018-04-03
申请号：US14783870
申请日：2015-08-21
IPC: H01L29/417 , H01L27/12 , H01L29/786 , H01L27/092 , H03K5/135 , H01L27/32
CPC classification number: H01L27/1222 , H01L27/092 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L29/41733 , H01L29/78603 , H01L29/78606 , H01L29/78633 , H01L29/78648 , H01L29/78675 , H03K5/135
Abstract: A control circuit of a thin film transistor, comprising: a substrate; a silicon nitride layer disposed on the substrate; a silicon dioxide layer disposed on the silicon nitride layer; a light shielding layer disposed inside the silicon nitride layer, which comprising a first light shielding region and a second light shielding region; at least one N type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; at least one P type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region; each of the N type metal oxide semiconductor and the P type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer synchronized with a second control signal received by the light shielding layer in voltage variation.
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公开(公告)号：US09841832B2
公开(公告)日：2017-12-12
申请号：US14759268
申请日：2015-04-27
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Shihpo Chou , Gui Chen , Jingfeng Xue
IPC: G06F3/041 , G06F3/044 , G02F1/1333 , G02F1/1343 , G02F1/1362
CPC classification number: G06F3/0412 , G02F1/13338 , G02F1/134336 , G02F1/13439 , G02F1/136286 , G06F3/044
Abstract: A self-capacitive touch panel structure includes a touch detection chip and multiple self-capacitance electrodes arranged as a matrix and isolated with each other. Each self-capacitance electrode connected with the touch detection chip through a connection line. Each self-capacitance electrode electrically connected with a corresponding connection line through at least one via hole. Wherein, a group of connection lines connected with a same column of the multiple self-capacitance electrodes are divided into an odd number group and an even number group, the connection lines in the odd number group are sequentially connected with corresponding self-capacitance electrodes from an terminal of the same column of the self-capacitance electrodes, and the connection lines in the even number group are sequentially connected with corresponding self-capacitance electrodes from another terminal of the same column of the self-capacitance electrodes. An in-cell touch panel and a liquid crystal display including above structure are also disclosed.
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公开(公告)号：US10446094B2
公开(公告)日：2019-10-15
申请号：US15319755
申请日：2016-08-19
Inventor： Guanghui Hong , Gui Chen , Qiang Gong
IPC: G09G3/36 , G02F1/133 , G02F1/1362 , G09G3/00
Abstract: The present disclosure provides a gate driver on array (GOA) circuit, where the GOA circuit includes a GOA driving chip, a GOA driving signal line, an array substrate test chip, a test signal line, and a GOA protecting circuit. The GOA driving chip is used to generate a scan driving signal. The GOA driving signal line is used to transmit the scan driving signal to a corresponding scan line. The array substrate test chip is used to generate an array substrate test signal. The test signal line is used to transmit the array substrate test signal to the corresponding scan line. The GOA protecting circuit is arranged between the GOA driving signal line and the test signal line.
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公开(公告)号：US10262618B2
公开(公告)日：2019-04-16
申请号：US15021461
申请日：2016-02-26
IPC: G09G3/36 , G02F1/13 , H03K17/687
Abstract: A GOA circuit includes GOA circuit units. Each GOA circuit has a holding module A first transistor and a second transistor in the holding module holds the voltage imposed on the first control node to be at high voltage level. Also, the transistors form a direct current passage between the first control node and a first fixed voltage at high voltage level so the voltage imposed on the first control node is not lowered due to electricity leakage. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.
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