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公开(公告)号:US12183752B2
公开(公告)日:2024-12-31
申请号:US17419294
申请日:2021-05-24
Inventor: Fuhsiung Tang , Fan Gong , Fei Ai , Jiyue Song
IPC: H01L27/146
Abstract: An array substrate is disclosed. The array substrate includes a semiconductor layer integrated with a PIN photoelectric diode and an active area. The PIN photoelectric diode includes a P-type semiconductor area, an N-type semiconductor area, and an I-type semiconductor area defined between the P-type semiconductor area and the N-type semiconductor area. A gate electric current is introduced at a location corresponding to the I-type semiconductor area, so as to enhance light sensitivity.
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公开(公告)号:US12140845B2
公开(公告)日:2024-11-12
申请号:US17976805
申请日:2022-10-30
IPC: G02F1/1368 , G02F1/1362 , H10K59/131
Abstract: The present disclosure provides a display panel and a display device. The display panel includes a thin film transistor; and further includes a substrate; a first metal layer disposed on the substrate and including a gate of the thin film transistor; an active layer disposed on a side of the first metal layer away from the substrate and including an active portion of the thin film transistor; a spacer layer disposed on a side of the active layer away from the first metal layer and including a plurality of contact holes; a second metal layer disposed on a side of the spacer layer away from the active layer and including a source and a drain of the thin film transistor; an orthographic projection of the gate electrode on the substrate covers an orthographic projection of at least part of the contact holes on the substrate.
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公开(公告)号:US12136396B2
公开(公告)日:2024-11-05
申请号:US17430058
申请日:2021-06-08
Inventor: Chao Tian , Yanqing Guan , Guanghui Liu , Fei Ai
IPC: G09G3/3266 , G09G3/20 , G09G3/36
Abstract: The present application provides a display panel and a display device. An N-th auxiliary unit is arranged in a display area of the display panel. An output end of the N-th auxiliary unit is connected to an N-th scan line. By connecting the auxiliary unit arranged in the display area to the corresponding scan line, a falling edge of a scan signal transmitted in the scan line can have sharp falling or a rising edge of the scan signal can have sharp rising, which can alleviate a signal distortion problem caused by transmission delay in the display area.
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公开(公告)号:US12072594B2
公开(公告)日:2024-08-27
申请号:US17607852
申请日:2021-09-08
Inventor: Zhilin Wu , Tao Ma , Dewei Song , Fei Ai
IPC: G02F1/1368 , G02F1/1333 , G02F1/1343 , G02F1/1362
CPC classification number: G02F1/136295 , G02F1/13338 , G02F1/1343 , G02F1/136209 , G02F1/136227 , G02F1/1368
Abstract: The present application discloses a display panel and an electrical terminal. The display panel includes: an underlay; an array driver layer located on the underlay and including a gate electrode layer and a source and drain electrode layer; a signal line including an adaptor portion located in the non-display region, wherein the adaptor portion includes a first wire section disposed in a same layer with the gate electrode layer, a second wire section disposed in a same layer with the source and drain electrode layer, and a bridge portion electrically connected to the first wire section and the second wire section; wherein the first wire section, the second wire section, and the bridge portion are disposed in different layers.
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公开(公告)号:US12027543B2
公开(公告)日:2024-07-02
申请号:US17281268
申请日:2021-03-11
Inventor: Fuhsiung Tang , Fan Gong , Fei Ai , Jiyue Song
IPC: H01L27/146 , G06V40/13
CPC classification number: H01L27/14612 , G06V40/1318 , H01L27/14678
Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, and a switch component and a light-sensing component adjacent to each other and disposed on the substrate. The switch component includes a first semiconductor disposed on the substrate. The light-sensing component includes a second semiconductor disposed on a same layer as the first semiconductor and a light-sensing electrode disposed on a side of the second semiconductor away from the substrate and connected to the second semiconductor. The light-sensing electrode and the second semiconductor constitute a Schottky knot.
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公开(公告)号:US12020614B2
公开(公告)日:2024-06-25
申请号:US17441303
申请日:2021-08-06
Inventor: Haiming Cao , Chao Tian , Yanqing Guan , Fei Ai , Guanghui Liu
IPC: G09G3/3266 , G09G3/20
CPC classification number: G09G3/20 , G09G2310/0267 , G09G2310/08 , G09G2320/045
Abstract: A gate drive circuit and a display panel are provided. A pull-up module and a pull-down module of the gate drive circuit output a constant-voltage high potential to a second node, a third node, and a n-th stage gate drive signal through a P-type thin film transistor and output constant-voltage low potential through a N-type thin film transistor to the second node, the third node, and an n-th gate drive signal, thereby improving the stability of the output signal of the thin film transistor connected to the gate drive circuit and the key node.
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公开(公告)号:US12243458B2
公开(公告)日:2025-03-04
申请号:US17596876
申请日:2021-12-14
Inventor: Chao Tian , Yanqing Guan , Guanghui Liu , Fei Ai
Abstract: The present application provides a display panel and an electronic device. The electronic device comprises the display panel. The display panel comprises a gate driving unit, a first auxiliary driving unit and scan lines. The first auxiliary driving unit rapidly pulls down the falling edge of the scan signal transmitted in the scan line to reduce the delay of the falling edge of the scan line. Thus, the number of gate driving units in the display panel can be reduced, thereby reducing the width of the frame of the display panel and the electronic device.
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公开(公告)号:US12164195B2
公开(公告)日:2024-12-10
申请号:US17925028
申请日:2022-11-08
Inventor: Fei Ai , Dewei Song , Chengzhi Luo
IPC: G02F1/1335 , G02F1/1333 , G02F1/1368
Abstract: A display panel and a manufacturing method thereof, and a display device are provided. The display panel includes a backlight module and an array substrate. The array substrate includes an insulation structure is located in the opening region. A first groove is defined at a side of the insulation structure away from the backlight module. A first insulation layer and a second insulation layer are filled in the first groove. The second insulation layer is located on a side of the first insulation layer close to the backlight module, and a refractive index of the second insulation layer is less than a refractive index of the first insulation layer.
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公开(公告)号:US12087782B2
公开(公告)日:2024-09-10
申请号:US17260982
申请日:2020-11-24
Inventor: Fei Ai , Jiyue Song , Dewei Song
IPC: H01L27/146 , G02F1/1343 , G02F1/1362 , G02F1/1368 , G06F3/041 , G06V40/13
CPC classification number: H01L27/14603 , G02F1/13439 , G02F1/136227 , H01L27/14692 , G02F1/134363 , G02F1/13685 , G06F3/0412 , G06V40/1318 , H01L27/14612 , H01L27/14643
Abstract: An array substrate, a display panel, and an electronic device are provided. The array substrate includes a substrate, a first conductive layer including a first connection part, a fourth insulating layer disposed on the first conductive layer and provided with a second via, and a second conductive layer disposed on the fourth insulating layer and in the second via. The second conductive layer includes a second electrode, and the second electrode is connected to the first connection part through the second via.
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公开(公告)号:US12033424B2
公开(公告)日:2024-07-09
申请号:US17052110
申请日:2020-08-14
Inventor: Jianfeng Yuan , Fan Gong , Fei Ai , Jiyue Song , Dewei Song , Shiyu Long
IPC: G06V40/13 , G02F1/1333 , G02F1/1335 , G02F1/1339 , G02F1/1343 , G02F1/1362 , G02F1/1368 , G06F3/041 , G06F3/044 , H01L31/0376 , H01L31/113
CPC classification number: G06V40/1318 , G02F1/13338 , G02F1/133514 , G02F1/1339 , G02F1/134309 , G02F1/136286 , G02F1/1368 , G06F3/0412 , G06F3/0445 , H01L31/03762 , H01L31/1136
Abstract: A light-sensitive sensor, an array substrate, and an electronic equipment are provided. The light-sensitive sensor includes a third metal layer, a second semiconductor layer, and a fourth metal layer. The third metal layer includes a second gate. The second semiconductor layer includes conductive portions, and the conductive portions are disposed at both ends of the second semiconductor layer. The fourth metal layer disposed on the second semiconductor layer, and the fourth metal layer includes a second source and a second drain.
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