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1.发明申请公开(公告)号：US20180053834A1
公开(公告)日：2018-02-22
申请号：US15031753
申请日：2016-02-25
Inventor： Zhandong Zhang , Fuhsiung Tang
IPC: H01L29/66 , H01L21/265 , H01L29/786 , H01L27/085 , H01L27/32
CPC classification number: H01L29/66492 , H01L21/26506 , H01L21/77 , H01L27/085 , H01L27/12 , H01L27/1203 , H01L27/1218 , H01L27/1229 , H01L27/1285 , H01L27/32 , H01L27/3225 , H01L29/66757 , H01L29/78618 , H01L29/78672
Abstract: The present invention provides a manufacture method of a Low Temperature Poly-silicon TFT substrate and a Low Temperature Poly-silicon TFT substrate, in which by locating one heat sink layer under the amorphous silicon layer in advance, the difference of the crystallizations of the polysilicons in the drive area and the display area can exist after implementing an Excimer Laser Annealing process to the amorphous silicon layer, and in the drive area, the polysilicon with the larger lattice dimension is formed to promote the electron mobility; the fractured crystals can be achieved in the crystallization process of the display area to form the polysilicon with the smaller lattice dimension for ensuring the uniformity of the grain boundary and raising the uniformity of the current, and thus, the electrical property demands for the different TFTs can be satisfied to raise the light uniformity of the OLED.
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Patent Agency Ranking
公开(公告)号：US20170200750A1
公开(公告)日：2017-07-13
申请号：US15137001
申请日：2016-04-25
Inventor： Yuanfu Liu , Fuhsiung Tang
IPC: H01L27/12 , G02F1/1339 , G02F1/1333 , G02F1/1368 , H01L21/311 , G06F3/041
CPC classification number: H01L27/1288 , G02F1/13338 , G02F1/1339 , G02F2001/133357 , G02F2001/133388 , G02F2001/13606 , G02F2001/136236 , G02F2202/28 , G06F3/0412 , G06F3/044 , G06F2203/04103 , H01L21/31144 , H01L27/1248 , H01L27/1259
Abstract: Provided is a method for manufacturing an array substrate, in which a planarization layer mask includes a strip pattern that is provided for forming a groove and has two opposite sides along which taper modification patterns are provided so as to reduce taper of a groove formed in a planarization layer, making a slope thereof less steep, thereby preventing shorting of signal lines caused by residues of metal or ITO in a subsequent operation and thus increasing product yield. For the groove associated portion of an array substrate involving an in-cell touch structure, there is no need to change line for the touch sensing lines so as to lower down the difficulty of the operation and increase product yield.
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公开(公告)号：US12183752B2
公开(公告)日：2024-12-31
申请号：US17419294
申请日：2021-05-24
Inventor： Fuhsiung Tang , Fan Gong , Fei Ai , Jiyue Song
IPC: H01L27/146
Abstract: An array substrate is disclosed. The array substrate includes a semiconductor layer integrated with a PIN photoelectric diode and an active area. The PIN photoelectric diode includes a P-type semiconductor area, an N-type semiconductor area, and an I-type semiconductor area defined between the P-type semiconductor area and the N-type semiconductor area. A gate electric current is introduced at a location corresponding to the I-type semiconductor area, so as to enhance light sensitivity.
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公开(公告)号：US12027543B2
公开(公告)日：2024-07-02
申请号：US17281268
申请日：2021-03-11
Inventor： Fuhsiung Tang , Fan Gong , Fei Ai , Jiyue Song
IPC: H01L27/146 , G06V40/13
CPC classification number: H01L27/14612 , G06V40/1318 , H01L27/14678
Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, and a switch component and a light-sensing component adjacent to each other and disposed on the substrate. The switch component includes a first semiconductor disposed on the substrate. The light-sensing component includes a second semiconductor disposed on a same layer as the first semiconductor and a light-sensing electrode disposed on a side of the second semiconductor away from the substrate and connected to the second semiconductor. The light-sensing electrode and the second semiconductor constitute a Schottky knot.
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公开(公告)号：US11747691B2
公开(公告)日：2023-09-05
申请号：US17281935
申请日：2021-01-29
Inventor： Fuhsiung Tang , Yanqing Guan , Congxing Yang
IPC: G02F1/1368 , G02F1/1362 , G09G3/36
CPC classification number: G02F1/1368 , G02F1/136286 , G09G3/3677
Abstract: A display panel and a display device are disclosed. The display panel includes a transistor disposed in the non-display area. The transistor includes a charge inducing layer, and a first insulating layer, an active layer, a second insulating layer, and a gate electrode all disposed on the charge inducing layer, so that the actively layer, the gate electrode, and the charge inducing layer collectively form a capacitance system, which benefits extending of the conduction time of the transistor, thereby giving a boost to an increase in a charging rate of the data line, and ensuring a smooth display of the display panel.
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公开(公告)号：US10269925B2
公开(公告)日：2019-04-23
申请号：US15031753
申请日：2016-02-25
Inventor： Zhandong Zhang , Fuhsiung Tang
IPC: H01L29/66 , H01L21/265 , H01L29/786 , H01L21/77 , H01L27/12 , H01L27/32 , H01L27/085
Abstract: The present invention provides a manufacture method of a Low Temperature Poly-silicon TFT substrate and a Low Temperature Poly-silicon TFT substrate, in which by locating one heat sink layer under the amorphous silicon layer in advance, the difference of the crystallizations of the polysilicons in the drive area and the display area can exist after implementing an Excimer Laser Annealing process to the amorphous silicon layer, and in the drive area, the polysilicon with the larger lattice dimension is formed to promote the electron mobility; the fractured crystals can be achieved in the crystallization process of the display area to form the polysilicon with the smaller lattice dimension for ensuring the uniformity of the grain boundary and raising the uniformity of the current, and thus, the electrical property demands for the different TFTs can be satisfied to raise the light uniformity of the OLED.
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