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公开(公告)号：US11838019B2
公开(公告)日：2023-12-05
申请号：US16965367
申请日：2020-06-23
Inventor： Chao Tian
IPC: G06V40/13 , H03K17/94 , H01L27/146
CPC classification number: H03K17/941 , G06V40/1318 , H01L27/14612 , H01L27/14643
Abstract: An optical fingerprint identification circuit and a display panel are provided. The optical fingerprint identification circuit adds a reset unit at the gate of the driving transistor. The anode of the photodiode is electrically connected to the scan line. The optical fingerprint identification circuit could effectively avoid the reverse breakdown risk of the photodiode while realizing the fingerprint identification. It could reduce the requirement for the reverse breakdown voltage of the photodiode and requirement for the performance of the sensor. Furthermore, the circuit structure is simpler and the number of the TFTs is reduced. This improves the integration of the circuit.
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公开(公告)号：US11817044B1
公开(公告)日：2023-11-14
申请号：US18050935
申请日：2022-10-28
Inventor： Haiming Cao , Chao Tian , Fei Ai , Guanghui Liu
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2300/0852 , G09G2310/027 , G09G2320/0233 , G09G2320/0633
Abstract: The present application provides a pixel driving circuit and a display panel. The pixel driving circuit includes an amplitude regulating module and a pulse width modulation module, where the amplitude regulating module and the pulse width modulation module are both electrically connected to a first node, so that the pulse width modulation module and the amplitude modulation module are configured to cooperate with a first data signal and a second data signal, respectively, to realize regulation of both the pulse width and the amplitude of the valid pulse of the driving current signal for driving the light emitting device to emit light. As such, the valid pulse of the driving current signal has different pulse widths and different amplitudes under correspondingly different gray scale states, so that the light emitting brightness and the light emitting duration of the light emitting device under correspondingly different gray scale states are different.
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公开(公告)号：US11362118B2
公开(公告)日：2022-06-14
申请号：US16756350
申请日：2019-11-15
Inventor： Juncheng Xiao , Chao Tian , Yanqing Guan , Haiming Cao
IPC: H01L27/00 , H01L27/12 , G09G3/3225 , G09G3/36
Abstract: The present invention provides an array substrate, a manufacturing method thereof, and a display panel. Orthographic projections of channel layers of two types of thin film transistors in a design of a driving circuit on the array substrate at least partially overlap, that is, two thin film transistors are stacked on top of each other, thereby facilitating a narrow border design of the display panel. In addition, a channel layer of one of the thin film transistors is an amorphous oxide semiconductor layer, which can reduce node leakage in the driving circuit, which is conducive to improving circuit stability and reducing power consumption.
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公开(公告)号：US11239262B2
公开(公告)日：2022-02-01
申请号：US16630916
申请日：2019-11-06
Inventor： Juncheng Xiao , Chao Tian
IPC: H01L27/12 , H01L27/142 , H01L27/20
Abstract: An embodiment of the present invention discloses an array substrate, a method of fabricating the same, and a display panel. Compared with the conventional technology, the present invention combines a sensing material with thin film transistors to prepare a sensing layer on the thin film transistors, and since the thin film transistors can be formed by a large-area preparation, the sensors can be formed by a large-area preparation accordingly, thereby improving a performance of the sensors and reducing the production cost of the sensors.
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公开(公告)号：US11152490B2
公开(公告)日：2021-10-19
申请号：US16097891
申请日：2018-08-01
Inventor： Juncheng Xiao , Chao Tian
IPC: H01L29/00 , H01L29/66 , H01L21/8234 , H01L27/12 , H01L29/786
Abstract: The present disclosure provides an array substrate and a method for manufacturing the same. The method includes providing a substrate, and forming a polysilicon layer, a gate insulating layer, a second buffer layer, a patterned second metal layer, and a third buffer layer on the substrate in turn; forming a through-hole by a mask process, wherein the through-hole passes through the passivation layer, the third buffer layer, the second buffer layer, and the gate insulating layer to contact the polysilicon layer.
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Patent Agency Ranking
公开(公告)号：US10977979B1
公开(公告)日：2021-04-13
申请号：US16965360
申请日：2020-06-19
Inventor： Juncheng Xiao , Chao Tian , Yanqing Guan , Yongxiang Zhou
IPC: G09G3/20
Abstract: A GOA circuit and a display panel are provided. The GOA circuit includes N stage GOA units, and an n-th stage GOA unit comprises a forward scan control module, a reverse scan control module, a pull-up module, a pull-down module, and a function module, wherein 2
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公开(公告)号：US10885862B2
公开(公告)日：2021-01-05
申请号：US16342207
申请日：2018-08-16
Inventor： Xin Zhang , Juncheng Xiao , Chao Tian , Yanqing Guan
IPC: G09G3/36
Abstract: A GOA circuit, a display panel and a display apparatus are provided. The GOA circuit includes: a forward/backward scanning control module configured to control, according to a forward scanning control signal or a backward scanning control signal, the GOA circuit to perform forward scanning or backward scanning, the level of an output signal from the forward/backward scanning control module being greater than a preset value; and, an output control module configured to control, according to a clock signal in a current level, the output of a gate driving signal in the current level.
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公开(公告)号：US12165609B2
公开(公告)日：2024-12-10
申请号：US17613579
申请日：2021-09-06
Inventor： Haiming Cao , Chao Tian , Yanqing Guan , Fei Ai , Guanghui Liu , Zhifu Li
IPC: G09G3/36
Abstract: The present application provides a display panel in which transistors in an input pull-up module, a stage transfer output module, and an output pull-up module are provided as P-type low temperature polysilicon thin film transistors, and a transistor in an output pull-down module is provided as an N-type metal oxide thin film transistor.
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公开(公告)号：US12046172B2
公开(公告)日：2024-07-23
申请号：US17434790
申请日：2021-07-15
Inventor： Mingyue Li , Chao Tian , Yanqing Guan , Fei Ai , Guanghui Liu
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/0267 , G09G2310/0283
Abstract: The present application discloses a gate drive circuit and a display device. The gate drive circuit includes a plurality of cascaded gate drive units, in which one of the gate drive units includes a first layout, an input module and a pull-up module. By receiving a potential changeable signal by the gate of a first transistor or the gate of a second thin-film transistor, it can alleviate or avoid current leakage caused when a first node keeps at a same voltage level for a long time, thereby improving the stability of the potential of the first node.
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公开(公告)号：US11355081B1
公开(公告)日：2022-06-07
申请号：US17261014
申请日：2020-06-30
Inventor： Chao Tian
IPC: G09G3/36
Abstract: A gate driver on array (GOA) circuit, a display panel and a display device are provided. The GOA circuit includes m cascaded GOA units. An nth-stage GOA unit includes a second feedback module. The second feedback module, electrically connected to the second node of the nth-stage GOA unit, a first node of the (n−1)th-stage GOA unit, the clock signal of the (n+1)th-stage GOA unit, a gate driving signal of the nth-stage GOA unit and the constant low voltage signal, to pull down voltage applied on a second node of the nth-stage GOA unit. The one-way feedback could achieve the linear design more easily, raise the circuit stability, and thus the GOA circuit could be integrated in the display panel more easily to achieve the design of placing the GOA circuit in the active area.
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