公开(公告)号：US20220384601A1

公开(公告)日：2022-12-01

申请号：US17818918

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/78

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20230141093A1

公开(公告)日：2023-05-11

申请号：US18149130

申请日：2023-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu LIN ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Tzer-Min SHEN ,  Fu-Ting YEN ,  Gary CHAN ,  Keng-Chu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/3065

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/823418

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

公开(公告)号：US20220037500A1

公开(公告)日：2022-02-03

申请号：US17197892

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li WANG ,  Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Tzer-Min SHEN ,  Pinyen LIN

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

公开(公告)号：US20190237464A1

公开(公告)日：2019-08-01

申请号：US16380818

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Kuan-Lun CHENG ,  Chih-Hao WANG ,  Sai-Hooi YEONG ,  Tzer-Min SHEN ,  Chi-Hsing HSU

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/26506 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/40111 ,  H01L29/511 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods of forming a FET including a substrate having a first fin and a second fin extending therefrom. A high-k gate dielectric layer and a ferroelectric insulator layer are deposited over the first fin and the second fin. In some embodiments, a dummy gate layer is deposited over the ferroelectric insulator layer over the first fin and the second fin to form a first gate stack over the first fin and a second gate stack over the second fin. The dummy gate layer of the first gate stack is then removed (while maintaining the ferroelectric insulator layer) to form a first trench. And the dummy gate layer and the ferroelectric insulator layer of the second gate stack are removed to form a second trench. At least one metal gate layer is formed in the first trench and the second trench.

公开(公告)号：US20150194485A1

公开(公告)日：2015-07-09

申请号：US14661237

申请日：2015-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mahaveer Sathaiya DHANYAKUMAR ,  Wei-Hao WU ,  Tsung-Hsing YU ,  Chia-Wen LIU ,  Tzer-Min SHEN ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/26586 ,  H01L21/76232 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract translation: 设置在浅沟槽隔离（STI）结构之间的MOSFET包括形成在衬底表面上并在STI结构的向内延伸的突出部上延伸的外延硅层。 因此，MOSFET的栅极宽度是外延硅层的宽度，并且大于STI结构之间的原始衬底表面的宽度。 外延硅层形成在预先掺杂的沟道上，并且在沉积时未被掺杂。 可以使用热激活操作来将掺杂剂杂质驱动到由外延硅层占据的晶体管沟道区域中，但是外延硅层与栅极电介质相交的沟道位置处的掺杂剂浓度最小化。