公开(公告)号：US20240162083A1

公开(公告)日：2024-05-16

申请号：US18421155

申请日：2024-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chen-Han WANG ,  Keng-Chu LIN ,  Tetsuji UENO ,  Ting-Ting CHEN

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/7682 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76832 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6653

Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.

公开(公告)号：US20210287904A1

公开(公告)日：2021-09-16

申请号：US17333639

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Ting-Ting CHEN ,  Teng-Chun TSAI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3205

Abstract: A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

公开(公告)号：US20210193506A1

公开(公告)日：2021-06-24

申请号：US16937237

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chen-Han WANG ,  Keng-Chu LIN ,  Tetsuji UENO ,  Ting-Ting CHEN

IPC: H01L21/768 ,  H01L29/66

Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.

公开(公告)号：US20230268387A1

公开(公告)日：2023-08-24

申请号：US18311066

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Tetsuji UENO ,  Ting-Ting CHEN ,  Chen-Han WANG ,  Keng-Chu LIN

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/02447 ,  H01L21/02529 ,  H01L29/7851 ,  H01L29/41791 ,  H01L29/66795 ,  H01L27/0886

Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.

公开(公告)号：US20230146366A1

公开(公告)日：2023-05-11

申请号：US18152952

申请日：2023-01-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Ting-Ting CHEN ,  Teng-Chun TSAI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3205

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/32135 ,  H01L21/02118 ,  H01L29/6656 ,  H01L21/31116 ,  H01L21/02282 ,  H01L21/0206 ,  H01L21/28556 ,  H01L21/31058 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/32051 ,  H01L29/66795 ,  H01L21/32

Abstract: A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.

公开(公告)号：US20220285492A1

公开(公告)日：2022-09-08

申请号：US17192134

申请日：2021-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Ting CHEN ,  Chen-Han WANG ,  Keng-Chu LIN ,  Shuen-Shin LIANG ,  Tsu-Hsiu PERNG ,  Tsai-Jung HO ,  Tsung-Han KO ,  Tetsuji UENO ,  Yahru CHENG

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

公开(公告)号：US20210193799A1

公开(公告)日：2021-06-24

申请号：US17100533

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chen-Han WANG ,  Keng-Chu LIN ,  Tetsuji UENO ,  Ting-Ting CHEN

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.

公开(公告)号：US20190164762A1

公开(公告)日：2019-05-30

申请号：US16122235

申请日：2018-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Ting-Ting CHEN ,  Teng-Chun TSAI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105

Abstract: A method includes forming a gate stack and an interlayer dielectric (ILD) over a substrate, wherein the interlayer dielectric is adjacent to the gate stack; forming an inhibitor covering the interlayer dielectric such that the gate stack is exposed from the inhibitor; performing a deposition process to form a conductive layer over the gate stack until the conductive layer starts to form on the inhibitor, in which the deposition process has a deposition selectivity for the gate stack with respect to the inhibitor; and performing an etching process to remove a portion of the conductive layer over the inhibitor.