知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.015 seconds)

    Gate structures for semiconductor devices
    2.
    发明授权
    Gate structures for semiconductor devices 有权

    公开(公告)号：US11049937B2

    公开(公告)日：2021-06-29

    申请号：US16657017

    申请日：2019-10-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Chun-I Wu ,  Huang-Lin Chao

    IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

    Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

    Work function layers for transistor gate electrodes
    3.
    发明授权
    Work function layers for transistor gate electrodes 有权

    公开(公告)号：US11183574B2

    公开(公告)日：2021-11-23

    申请号：US16690645

    申请日：2019-11-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Liang Cheng ,  Ziwei Fang ,  Chun-I Wu ,  Huang-Lin Chao

    IPC: H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

    Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

    NFET with Aluminum-Free Work-Function Layer and Method Forming Same
    8.
    发明申请
    NFET with Aluminum-Free Work-Function Layer and Method Forming Same 有权

    公开(公告)号：US20230020099A1

    公开(公告)日：2023-01-19

    申请号：US17648152

    申请日：2022-01-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui ,  Chun-I Wu ,  Huang-Lin Chao

    IPC: H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L21/285 ,  H01L21/28

    Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the silicon-containing layer, and the gate dielectric layer forming a gate stack.

    GATE STRUCTURES FOR SEMICONDUCTOR DEVICES
    9.
    发明申请
    GATE STRUCTURES FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210328018A1

    公开(公告)日：2021-10-21

    申请号：US17360451

    申请日：2021-06-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang CHENG ,  Chun-I Wu ,  Huang-Lin Chao

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

    Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

Patent Agency Ranking