公开(公告)号：US11961800B2

公开(公告)日：2024-04-16

申请号：US17814152

申请日：2022-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh

IPC分类号： H01L23/522 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/07 ,  H01L25/075 ,  H01L33/00 ,  H01L33/38 ,  H01L33/62 ,  H01L21/321 ,  H01L33/06 ,  H01L33/32

CPC分类号： H01L23/5226 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/11 ,  H01L24/89 ,  H01L25/072 ,  H01L25/0753 ,  H01L33/0093 ,  H01L33/38 ,  H01L33/62 ,  H01L21/3212 ,  H01L24/81 ,  H01L33/007 ,  H01L33/06 ,  H01L33/32 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/08225 ,  H01L2224/08501 ,  H01L2224/80006 ,  H01L2224/80815 ,  H01L2224/80895 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/005 ,  H01L2933/0066

摘要： A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

公开(公告)号：US20230245903A1

公开(公告)日：2023-08-03

申请号：US18297897

申请日：2023-04-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Wei-Yu Chen

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L25/18 ,  H01L21/683 ,  H01L23/498

CPC分类号： H01L21/568 ,  H01L24/28 ,  H01L23/49503 ,  H01L25/18 ,  H01L24/19 ,  H01L24/20 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105

摘要： A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

公开(公告)号：US11652063B2

公开(公告)日：2023-05-16

申请号：US16927126

申请日：2020-07-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Tsung-Shu Lin

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/48091 ,  H01L2924/00014

摘要： An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.

公开(公告)号：US20230014813A1

公开(公告)日：2023-01-19

申请号：US17952681

申请日：2022-09-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC分类号： G02B6/42 ,  H01L23/00

摘要： A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

公开(公告)号：US11508695B2

公开(公告)日：2022-11-22

申请号：US17195903

申请日：2021-03-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

摘要： An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.

公开(公告)号：US20220361332A1

公开(公告)日：2022-11-10

申请号：US17815373

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Hsien Hsieh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Li-Han Hsu ,  Wei-Cheng Wu

IPC分类号： H05K1/11 ,  H01L23/00 ,  H05K1/18

摘要： A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

公开(公告)号：US20220359470A1

公开(公告)日：2022-11-10

申请号：US17815390

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  An-Jhih Su ,  Wei-Yu Chen ,  Ying-Ju Chen ,  Tsung-Shu Lin ,  Chin-Chuan Chang ,  Hsien-Wei Chen ,  Wei-Cheng Wu ,  Li-Hsien Huang ,  Chi-Hsi Wu ,  Der-Chyang Yeh

IPC分类号： H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

摘要： A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

公开(公告)号：US20220165611A1

公开(公告)日：2022-05-26

申请号：US17650926

申请日：2022-02-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh ,  Jing-Cheng Lin ,  Hung-Jui Kuo

IPC分类号： H01L21/768 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

摘要： A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

公开(公告)号：US11069625B2

公开(公告)日：2021-07-20

申请号：US16231735

申请日：2018-12-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu

IPC分类号： H01L23/544 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

摘要： A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and forming a first dielectric layer over the package layer. The method further includes forming a first alignment mark and a second alignment mark over the first dielectric layer. The method includes forming a second dielectric layer over the first dielectric layer and removing a portion of the second dielectric layer to form a first trench to expose the first alignment mark, and to form a first opening to expose the second alignment.

公开(公告)号：US20210088723A1

公开(公告)日：2021-03-25

申请号：US16930558

申请日：2020-07-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC分类号： G02B6/122

摘要： A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.