公开(公告)号：US10665282B2

公开(公告)日：2020-05-26

申请号：US15573904

申请日：2016-05-16

申请人： TOHOKU UNIVERSITY

发明人： Hiroki Koike ,  Tetsuo Endoh

IPC分类号： G11C11/16

摘要： A memory circuit (11) includes: a memory cell (MCij) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MCij) to be read into a data voltage; a reference circuit (RCi) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MCij and being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RCi) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MCij) by comparing the data voltage with the reference voltage.

公开(公告)号：US09466363B2

公开(公告)日：2016-10-11

申请号：US14369974

申请日：2012-12-04

申请人： TOHOKU UNIVERSITY

发明人： Tetsuo Endoh ,  Takashi Ohsawa ,  Hiroki Koike ,  Takahiro Hanyu ,  Hideo Ohno

IPC分类号： G11C14/00 ,  G11C13/00 ,  G11C11/16 ,  G11C15/04 ,  G11C19/02 ,  H03K3/356 ,  H03K3/59 ,  H03K19/18 ,  G11C29/50

CPC分类号： G11C13/0038 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0081 ,  G11C15/046 ,  G11C19/02 ,  G11C29/50012 ,  H03K3/356139 ,  H03K3/59 ,  H03K19/18

摘要： An integrated circuit that does not involve increase in power consumption or decrease in switching probability during a write operation that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period τ has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of memory access of the basic circuit element 1A satisfies the following relation: τ>λ1/f1(0

公开(公告)号：US20140355330A1

公开(公告)日：2014-12-04

申请号：US14369974

申请日：2012-12-04

申请人： TOHOKU UNIVERSITY

发明人： Tetsuo Endoh ,  Takashi Ohsawa ,  Hiroki Koike ,  Takahiro Hanyu ,  Hideo Ohno

IPC分类号： G11C13/00

CPC分类号： G11C13/0038 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0081 ,  G11C15/046 ,  G11C19/02 ,  G11C29/50012 ,  H03K3/356139 ,  H03K3/59 ,  H03K19/18

摘要： An integrated circuit that does not involve increase in power consumption or decrease in switching probability that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period τ has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of information processing of the basic circuit element 1A satisfies the following relation: τ>λ1/f1(0

摘要翻译： 提供了当使用现有技术的STT-MTJ装置等的锁存电路以高速运行时，不涉及增加功耗或降低切换概率的集成电路。 集成电路1包括：存储元件1B，其中在写入信号被输入之后经过了指定的周期τ时发生写入; 以及作为构成电路并具有数据保持功能的基本装置的基本电路元件1A，其特征在于，在基本电路元件1A的信息处理的处理中的第一动作模式中的动作频率f1满足以下 关系：τ>λ1/ f1（0 <λ1＆nlE; 1）。

公开(公告)号：US11705176B2

公开(公告)日：2023-07-18

申请号：US17395210

申请日：2021-08-05

申请人： TOHOKU UNIVERSITY

发明人： Tetsuo Endoh ,  Hiroki Koike

IPC分类号： G11C11/16 ,  G11C29/04

CPC分类号： G11C11/1673 ,  G11C11/1659 ,  G11C29/04

摘要： A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.

公开(公告)号：US11514964B2

公开(公告)日：2022-11-29

申请号：US16770411

申请日：2018-12-10

申请人： TOHOKU UNIVERSITY

发明人： Hiroki Koike ,  Tetsuo Endoh

IPC分类号： G11C11/16

摘要： A storage circuit (11) includes memory cells (MCij), each of which includes an MTJ element, and reference cells (RCi), each of which includes a series circuit of an MTJ element set to a low-resistance state and a linear resistor (FR). A RW circuit (23j) that includes a sense amplifier is provided in each column of a memory cell array (21), and compares a data voltage on a corresponding bit line (BLj) with a reference voltage. The sense amplifier includes a pair of PMOS transistors to which the data voltage and the reference voltage are applied, a CMOS sense latch that is connected to a current path of the PMOS transistors.

公开(公告)号：US20180350419A1

公开(公告)日：2018-12-06

申请号：US15573904

申请日：2016-05-16

申请人： TOHOKU UNIVERSITY

发明人： Hiroki Koike ,  Tetsuo Endoh

IPC分类号： G11C11/16

CPC分类号： G11C11/1697 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory circuit (11) includes: a memory cell (MCij) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MCij) to be read into a data voltage; a reference circuit (RC1) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MCij and being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RCi) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MCij) by comparing the data voltage with the reference voltage.

公开(公告)号：US10783294B2

公开(公告)日：2020-09-22

申请号：US16323146

申请日：2017-08-03

申请人： TOHOKU UNIVERSITY

发明人： Masanori Natsui ,  Akira Tamakoshi ,  Takahiro Hanyu ,  Akira Mochizuki ,  Tetsuo Endoh ,  Hiroki Koike ,  Hideo Ohno

IPC分类号： G06F17/50 ,  G06F30/327 ,  G06F30/00 ,  G06F30/398

摘要： A circuit design support system, a circuit design support method, a circuit design support program, and a recording medium having the program recorded thereon are provided by which a design can be performed in consideration of the stochastic operation of the stochastic operation element and the influence caused by the stochastic operation of the stochastic operation element on the operation reliability of the circuit can be evaluated.

公开(公告)号：US11417378B2

公开(公告)日：2022-08-16

申请号：US17043257

申请日：2019-03-12

申请人： TOHOKU UNIVERSITY

发明人： Tetsuo Endoh ,  Shoji Ikeda ,  Hiroki Koike

IPC分类号： G11C11/16 ,  G11C13/00 ,  H01L43/02

摘要： An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.

公开(公告)号：US20210110857A1

公开(公告)日：2021-04-15

申请号：US17043257

申请日：2019-03-12

申请人： TOHOKU UNIVERSITY

发明人： Tetsuo Endoh ,  Shoji Ikeda ,  Hiroki Koike

IPC分类号： G11C11/16 ,  H01L43/02 ,  G11C13/00

摘要： An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.