Synchronous bootstrap half bridge rectifier

    公开(公告)号:US12062995B2

    公开(公告)日:2024-08-13

    申请号:US17873395

    申请日:2022-07-26

    CPC classification number: H02M7/219 H02M1/08

    Abstract: Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

    SEMICONDUCTOR DEVICE WITH GATE ELECTRICAL CONTACT FORMING JUNCTIONS HAVING DIFFERENT ENERGY BARRIER HEIGHTS TO GATE LAYER

    公开(公告)号:US20250048667A1

    公开(公告)日:2025-02-06

    申请号:US18361997

    申请日:2023-07-31

    Abstract: The present disclosure generally relates to a semiconductor device that includes a gate electrical contact that forms junctions with different energy barrier heights to a gate layer. In an example, a semiconductor device includes a semiconductor substrate, a drain electrical contact, a source electrical contact, a barrier layer, a gate layer, and a gate electrical contact. The drain and source electrical contacts are on the semiconductor substrate. The barrier layer is over a channel region of the semiconductor substrate between the drain and source electrical contacts. The gate layer is over the barrier layer. The gate layer includes first and second semiconductor portions. The gate electrical contact contacts the gate layer. The gate electrical contact includes first and second metal portions. The first and second metal portions form first and second junctions with the first and second semiconductor portions, respectively. The first and second junctions have different energy barrier heights.

    Enhancement mode startup circuit with JFET emulation

    公开(公告)号:US11621708B2

    公开(公告)日:2023-04-04

    申请号:US17314523

    申请日:2021-05-07

    Abstract: A startup circuit adapted to be coupled to an input voltage supply and operable to supply an output voltage at an output terminal, the startup circuit including: a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal adapted to be coupled to the input voltage supply and the second current terminal coupled to the output terminal; a precharge circuit having a first terminal, a second terminal and a third terminal, the second terminal adapted to be coupled to the input voltage supply and the third terminal coupled to the first control terminal; a current limiter coupled to the precharge circuit, the first control terminal and the second current terminal; a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to the precharge circuit and the second control terminal adapted to be coupled to a control signal; and a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the fifth current terminal coupled to the first control terminal and the third control terminal is adapted to be coupled to the control signal.

    SYNCHRONOUS BOOTSTRAP HALF BRIDGE RECTIFIER

    公开(公告)号:US20230038798A1

    公开(公告)日:2023-02-09

    申请号:US17873395

    申请日:2022-07-26

    Abstract: Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

    ENHANCEMENT MODE STARTUP CIRCUIT WITH JFET EMULATION

    公开(公告)号:US20200274530A1

    公开(公告)日:2020-08-27

    申请号:US16731847

    申请日:2019-12-31

    Abstract: A startup circuit includes an enhancement mode transistor with a drain coupled to a startup circuit input, a source coupled to a first node, and a gate coupled to a second node. The startup circuit includes a current limiting circuit that controls a current path between the second node and a startup circuit output node based on a current sense voltage signal representing a current through the enhancement mode transistor, and a voltage regulation circuit controls a voltage of the second node to regulate a startup circuit output voltage of the startup circuit output node.

    SYNCHRONOUS BOOTSTRAP HALF BRIDGE RECTIFIER
    10.
    发明公开

    公开(公告)号:US20240364232A1

    公开(公告)日:2024-10-31

    申请号:US18768245

    申请日:2024-07-10

    CPC classification number: H02M7/219 H02M1/08

    Abstract: Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

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