Invention Application
- Patent Title: ENHANCEMENT MODE STARTUP CIRCUIT WITH JFET EMULATION
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Application No.: US16731847Application Date: 2019-12-31
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Publication No.: US20200274530A1Publication Date: 2020-08-27
- Inventor: Michael Lueders , Johan Strydom , Cetin Kaya , Maik Peter Kaufmann
- Applicant: Texas Instruments Incorporated
- Main IPC: H03K17/22
- IPC: H03K17/22 ; H02M3/335 ; H02M1/36 ; H02M1/08

Abstract:
A startup circuit includes an enhancement mode transistor with a drain coupled to a startup circuit input, a source coupled to a first node, and a gate coupled to a second node. The startup circuit includes a current limiting circuit that controls a current path between the second node and a startup circuit output node based on a current sense voltage signal representing a current through the enhancement mode transistor, and a voltage regulation circuit controls a voltage of the second node to regulate a startup circuit output voltage of the startup circuit output node.
Public/Granted literature
- US11031933B2 Enhancement mode startup circuit with JFET emulation Public/Granted day:2021-06-08
Information query
IPC分类: