ENHANCEMENT MODE STARTUP CIRCUIT WITH JFET EMULATION
Abstract:
A startup circuit includes an enhancement mode transistor with a drain coupled to a startup circuit input, a source coupled to a first node, and a gate coupled to a second node. The startup circuit includes a current limiting circuit that controls a current path between the second node and a startup circuit output node based on a current sense voltage signal representing a current through the enhancement mode transistor, and a voltage regulation circuit controls a voltage of the second node to regulate a startup circuit output voltage of the startup circuit output node.
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