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    MULTILAYER PACKAGE SUBSTRATE WITH STRESS BUFFER
    1.
    发明公开
    MULTILAYER PACKAGE SUBSTRATE WITH STRESS BUFFER 审中-公开

    公开(公告)号：US20240112997A1

    公开(公告)日：2024-04-04

    申请号：US18482944

    申请日：2023-10-09

    Applicant: Texas Instruments Incorporated

    Inventor： Guangxu Li ,  Yiqi Tang ,  Rajen Manicon Murugan

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

    CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/16227

    Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

    Multilayer package substrate with stress buffer
    4.
    发明授权
    Multilayer package substrate with stress buffer 有权

    公开(公告)号：US11784113B2

    公开(公告)日：2023-10-10

    申请号：US17233110

    申请日：2021-04-16

    Applicant: Texas Instruments Incorporated

    Inventor： Guangxu Li ,  Yiqi Tang ,  Rajen Manicon Murugan

    IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

    CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/16227

    Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

    MULTILAYER PACKAGE SUBSTRATE WITH STRESS BUFFER
    6.
    发明申请
    MULTILAYER PACKAGE SUBSTRATE WITH STRESS BUFFER 有权

    公开(公告)号：US20210327794A1

    公开(公告)日：2021-10-21

    申请号：US17233110

    申请日：2021-04-16

    Applicant: Texas Instruments Incorporated

    Inventor： Guangxu Li ,  Yiqi Tang ,  Rajen Manicon Murugan

    IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

    Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

    MULTILEVEL PACKAGE SUBSTRATE FOR INTERLEVEL DIELECTRIC CRACK MITIGATION
    7.
    发明申请
    MULTILEVEL PACKAGE SUBSTRATE FOR INTERLEVEL DIELECTRIC CRACK MITIGATION 有权

    公开(公告)号：US20250006661A1

    公开(公告)日：2025-01-02

    申请号：US18344722

    申请日：2023-06-29

    Applicant: Texas Instruments Incorporated

    Inventor： Guangxu Li ,  Sylvester Ankamah-Kusi ,  Rajen Murugan

    IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

    Abstract: An electronic device includes a multilevel package substrate and a semiconductor die, where the multilevel package substrate has first and second levels in respective first and second planes in a stack, the first level including a first conductive feature, and the second level including a second conductive feature, and the semiconductor die has a conductive peripheral terminal, a conductive interior terminal, a peripheral region, and an interior region. The peripheral region laterally surrounds the interior region and extends laterally between the interior region and the lateral sides of the semiconductor die, the conductive peripheral terminal extends from the peripheral region to the first level, the conductive interior terminal extends from the interior region to the first level, the peripheral terminal is coupled to a peripheral contact portion of the first conductive feature, and the second level has no conductive feature under the peripheral contact portion.

    MICROELECTRONICS DEVICE PACKAGE AND METHODS
    8.
    发明公开
    MICROELECTRONICS DEVICE PACKAGE AND METHODS 审中-公开

    公开(公告)号：US20230411262A1

    公开(公告)日：2023-12-21

    申请号：US18335979

    申请日：2023-06-15

    Applicant: Texas Instruments Incorporated

    Inventor： Osvaldo Lopez ,  Jonathan Noquil ,  Jose Carlos Arroyo ,  Makarand R. Kulkarni ,  Guangxu Li

    IPC: H01L23/498 ,  H01L21/56

    CPC classification number: H01L23/49811 ,  H01L21/565 ,  H01L2021/60022 ,  H01L23/49822 ,  H01L21/563

    Abstract: An example microelectronics device package includes: a device mounting layer on an uppermost trace conductor layer on a device side surface of a package substrate, the uppermost trace conductor layer having a first pattern density. The device mounting layer includes a device connection conductor layer; a device mounting land conductor layer on the device connection conductor layer, the device mounting land conductor layer having device mounting land conductors directly contacting the conductors of the device connection conductor layer and having a second pattern density that is less than the first pattern density. A semiconductor die is flip chip mounted to the device mounting layer by solder joints between post connects extending from the semiconductor die and the device mounting land conductors. Mold compound covers the semiconductor die, and the device mounting layer, the mold compound is spaced from the uppermost trace conductor layer by the device mounting layer.

    PACKAGE SUBSTRATE WITH CTE MATCHING BARRIER RING AROUND MICROVIAS
    9.
    发明申请
    PACKAGE SUBSTRATE WITH CTE MATCHING BARRIER RING AROUND MICROVIAS 有权

    公开(公告)号：US20220254735A1

    公开(公告)日：2022-08-11

    申请号：US17679082

    申请日：2022-02-24

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal Mallory Williamson ,  Guangxu Li

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

    Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

    Package substrate with CTE matching barrier ring around microvias
    10.
    发明授权
    Package substrate with CTE matching barrier ring around microvias 有权

    公开(公告)号：US11270955B2

    公开(公告)日：2022-03-08

    申请号：US16205436

    申请日：2018-11-30

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal Mallory Williamson ,  Guangxu Li

    IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

    Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

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