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公开(公告)号：US12105131B2
公开(公告)日：2024-10-01
申请号：US18339250
申请日：2023-06-22
Inventor： Chi-Chang Lai , Kai-Yi Tang , Mill-Jer Wang
CPC classification number: G01R29/105 , G01R29/10 , G01R31/2822
Abstract: A testing device for testing an antenna is provided. The testing device includes a housing, an antenna module for holding the antenna and disposed under the housing, and a receiving module disposed on the housing. The antenna module includes a base and a flexible film disposed on the base. The receiving module includes a substrate, a coupling radiation element disposed on the substrate and a support disposed on the substrate and having an opening. The antenna is partially exposed from the opening.
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公开(公告)号：US12062586B2
公开(公告)日：2024-08-13
申请号：US18300576
申请日：2023-04-14
Inventor： Mill-Jer Wang , Tang-Jung Chiu , Chi-Chang Lai , Chia-Heng Tsai , Mirng-Ji Lii , Weil Liao
IPC: H01L21/66 , H01L23/552 , H01L27/01
CPC classification number: H01L22/34 , H01L23/552 , H01L27/01
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and multiple first conductive lines over the semiconductor substrate. The first conductive lines are not electrically connected to each other. The semiconductor device structure also includes multiple first magnetic structures wrapped around portions of the first conductive lines and multiple second conductive lines over the semiconductor substrate. The second conductive lines are electrically connected in series. The semiconductor device structure further includes multiple second magnetic structures wrapped around portions of the second conductive lines. A size of each of the second magnetic structures and a size of each of the first magnetic structures are substantially the same.
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公开(公告)号：US20230168296A1
公开(公告)日：2023-06-01
申请号：US18161839
申请日：2023-01-30
Inventor： Hao Chen , Mill-Jer Wang
CPC classification number: G01R31/275 , G01R1/0491 , G01R1/0466
Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.
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公开(公告)号：US10002829B2
公开(公告)日：2018-06-19
申请号：US14954207
申请日：2015-11-30
Inventor： Hao Chen , Chen-Hsiang Hsu , Hung-Chih Lin , Ching-Nen Peng , Mill-Jer Wang
IPC: H01L23/528 , G01R19/00 , G01R31/28 , H01L23/31 , H01L23/00 , H01L25/065 , H01L23/498
CPC classification number: H01L23/528 , G01R19/0092 , G01R31/2831 , G01R31/2884 , G01R31/2896 , H01L22/32 , H01L23/3107 , H01L23/49816 , H01L23/49827 , H01L24/06 , H01L24/09 , H01L24/14 , H01L24/17 , H01L25/0655 , H01L2224/02371 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/24137 , H01L2924/18162 , H01L2924/2064
Abstract: A semiconductor device is provided which comprises a semiconductive substrate and an interconnect on the substrate. The interconnect comprises a dielectric in an upper most level of the interconnect and a plurality of conductive pads where each of the plurality of conductive pads is at least partially exposed from the dielectric. The interconnect further includes a current sensor electrically coupled with at least one of the plurality of conductive pads.
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公开(公告)号：US09513332B2
公开(公告)日：2016-12-06
申请号：US14459801
申请日：2014-08-14
Inventor： Sandeep Kumar Goel , Mill-Jer Wang
IPC: G01R31/00 , G01R31/28 , G01R1/04 , G01R1/073 , G01R31/319
CPC classification number: G01R31/2889 , G01R1/0408 , G01R1/07342 , G01R31/31908
Abstract: A method of testing an integrated circuit die comprises partitioning a first probe card partition layout of the integrated circuit die having one or more sections comprising a first quantity of section types into a second probe card partition layout having a greater quantity of sections comprising a second quantity of section types, the second quantity of section types being less than the first quantity of section types. The method also comprises using one or more probe cards to test the sections in the second probe card partition layout, each of the one or more probe cards having a test contact pattern that corresponds with a test contact pattern of one of each section type included in the second probe card partition layout.
Abstract translation: 一种测试集成电路管芯的方法包括将具有一个或多个部分的集成电路管芯的第一探针卡分隔布局分成包括第一数量的部分类型到具有更大数量的部分的第二探针卡分配布局，所述部分包括第二数量 的截面类型，第二数量的截面类型小于第一数量的截面类型。 该方法还包括使用一个或多个探针卡来测试第二探针卡分区布局中的部分，所述一个或多个探针卡中的每一个具有与包括在每个部分类型之一的测试接触图案相对应的测试接触图案 第二个探针卡分区布局。
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Patent Agency Ranking
公开(公告)号：US20140176165A1
公开(公告)日：2014-06-26
申请号：US13724004
申请日：2012-12-21
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang , Chung-Sheng Yuan , Ching-Fang Chen , Wen-Wen Hsieh , Meng-Lin Chung
IPC: G01R31/26
CPC classification number: G01R31/2889 , G01R1/07378
Abstract: A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit.
Abstract translation: 三维集成电路测试装置包括：探针卡，被配置为将三维集成电路的测试装置与具有多个测试模块的自动测试设备板耦合，其中所述探针卡包括多个已知的 三维集成电路的良好裸片，三维集成电路的多个互连和多个探针触点，其中探针触点被配置为将探针卡与被测器件的测试触点耦合 三维集成电路。
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公开(公告)号：US20250062202A1
公开(公告)日：2025-02-20
申请号：US18451105
申请日：2023-08-17
Inventor： Chun-Yi Sung , Ta-Hsuan Lin , Hua-Wei Tseng , Mill-Jer Wang
IPC: H01L23/498 , H01L23/00 , H01L25/065
Abstract: A semiconductor die and methods of forming the same and a package structure are provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads over the semiconductor substrate, a passivation layer over the semiconductor substrate and partially covering the plurality of conductive pads, an interconnecting line disposed on the passivation layer, and a plurality of connectors disposed on and electrically connected to the plurality of conductive pads. Each of the plurality of connectors includes a stacked structure of a first conductive pillar and a second conductive pillar disposed directly on the first conductive pillar, wherein a span of the second conductive pillar is smaller than a span of the first conductive pillar, and an orthogonal projection of the second conductive pillar falls within an orthogonal projection of the first conductive pillar, and the interconnecting line is located beside and spaced apart from the plurality of connectors.
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公开(公告)号：US11335672B2
公开(公告)日：2022-05-17
申请号：US16937343
申请日：2020-07-23
Inventor： Hsiang-Tai Lu , Shuo-Mao Chen , Mill-Jer Wang , Feng-Cheng Hsu , Chao-Hsiang Yang , Shin-Puu Jeng , Cheng-Yi Hong , Chih-Hsien Lin , Dai-Jang Chen , Chen-Hua Lin
IPC: H01L25/00 , H01L23/538 , H01L23/31 , H01L23/00 , H01L25/10 , H01L21/48 , H01L21/56 , H01L21/66 , H01L23/498 , H01L23/522 , H01L23/053
Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.
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公开(公告)号：US11199576B2
公开(公告)日：2021-12-14
申请号：US16390779
申请日：2019-04-22
Inventor： Ming-Cheng Hsu , Mill-Jer Wang
IPC: G01R31/28
Abstract: A probe head and methods of testing a device using a probe head are provided. The probe head includes a first end connected to a first substrate. The first substrate is configured to be connected to a test head. The probe head also includes second end having a first inner recess surrounded by a first protrusion and a first plurality of probe needles connected to the first protrusion.
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公开(公告)号：US20210096173A1
公开(公告)日：2021-04-01
申请号：US16867999
申请日：2020-05-06
Inventor： Hao Chen , Mill-Jer Wang
IPC: G01R31/28
Abstract: A testing system includes a load board that includes a first circuit board, a first external connector attached to the first circuit board, and a thermal module configured to hold a system-on-wafer structure including a connector and a socket, a connector structure including a second circuit board, wherein the second circuit board is electrically connected to the first external connector, and a second external connector configured to connect to the connector of the system-on-wafer structure, and a test structure configured to connect to the socket of the system-on-wafer structure, the test structure including a third circuit board and pins, wherein adjacent pairs of pins of the test structure are electrically coupled through the third circuit board to form a continuous conductive path extending alternately between the system-on-wafer structure and the adjacent pairs of pins of the test structure.
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