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公开(公告)号:US20220342296A1
公开(公告)日:2022-10-27
申请号:US17810861
申请日:2022-07-06
发明人: WEI-CHUNG HU , CHI-TA LU , CHI-MING TSAI
IPC分类号: G03F1/70 , G06F30/398
摘要: A method for manufacturing a semiconductor device is provided. The method includes the following operations. A first layout including a plurality of first features is provided. A modified second layout is determined. The modified second layout includes a plurality of modified features separated from each other, and each of the plurality of modified features respectively overlaps each of the plurality of first features. The modified second layout is outputted to a photomask.
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公开(公告)号:US20210349389A1
公开(公告)日:2021-11-11
申请号:US17383287
申请日:2021-07-22
摘要: A method includes providing a first design layout including cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; training a model based on a layout-dependent parameter of a second design layout; and updating a second cell based on the data set and the model to provide a second updated cell. The model includes an input layer, a hidden layer and an output layer. Training the model includes obtaining converged values of nodes of the hidden layer. Obtaining converged values of nodes of the hidden layer includes providing information on edge segments before and after lithography enhancement to the input layer and the output layer, respectively, until values of nodes of the hidden layer attains convergence in terms of a cost function.
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公开(公告)号:US20210064808A1
公开(公告)日:2021-03-04
申请号:US16937398
申请日:2020-07-23
发明人: CHI-TA LU , CHIA-HUI LIAO , YIHUNG LIN , CHI-MING TSAI
IPC分类号: G06F30/392 , G06F30/398
摘要: A method, a non-transitory computer-readable storage medium and a system for adjusting a design layout are provided. The method includes: receiving a design layout including a feature in a peripheral region of the design layout; determining a first compensation value associated with the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout by modifying a shape of the feature according to the compensation value.
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公开(公告)号:US20210005552A1
公开(公告)日:2021-01-07
申请号:US17026283
申请日:2020-09-20
发明人: CHI-TA LU , CHI-MING TSAI
IPC分类号: H01L23/528 , H01L21/768
摘要: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.
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公开(公告)号:US20200098689A1
公开(公告)日:2020-03-26
申请号:US16212112
申请日:2018-12-06
发明人: CHI-TA LU , CHI-MING TSAI
IPC分类号: H01L23/528 , H01L23/00 , H01L21/768
摘要: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via parallel to the first surface of the substrate, wherein the first conductive line includes a second surface at least partially interfaced with the conductive via, the second surface of the first conductive line includes a first end, a second end opposite to the first end and a first central axis passing through the first end and the second end, the cross section of the conductive via includes a second central axis parallel to the first central axis and a third central axis orthogonal to the second central axis.
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公开(公告)号:US20240143887A1
公开(公告)日:2024-05-02
申请号:US18404892
申请日:2024-01-05
发明人: CHI-TA LU , CHIA-HUI LIAO , YIHUNG LIN , CHI-MING TSAI
IPC分类号: G06F30/392 , G06F30/398
CPC分类号: G06F30/392 , G06F30/398 , G06F2111/20
摘要: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones; and adjusting line widths in the compensation zones of the feature according to the compensation values associated with the respective compensation zones.
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公开(公告)号:US20230341765A1
公开(公告)日:2023-10-26
申请号:US18344844
申请日:2023-06-29
CPC分类号: G03F1/70 , G03F1/36 , G03F1/22 , G03F7/2004 , G06N20/00 , G06F30/392
摘要: A method includes: providing a first design layout including a plurality of cells; updating a first cell of the plurality of cells using optical proximity correction to provide a first updated cell and a data set; and updating a second cell from remaining cells in the first design layout based on the data set and a model without involvement of optical proximity correction to provide a second updated cell, wherein the model includes hidden layers including nodes and is trained to obtaining converged values of the nodes of the hidden layers through providing a mapping of edge segments before lithography enhancement and edge segments after lithography enhancement using optical proximity correction, and wherein at least one of the providing, and updating is executed by one or more processors.
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公开(公告)号:US20200097631A1
公开(公告)日:2020-03-26
申请号:US16141112
申请日:2018-09-25
发明人: CHIN-MIN HUANG , CHING-HUNG LAI , JIA-GUEI JOU , YIN-CHUAN CHEN , CHI-MING TSAI
IPC分类号: G06F17/50 , H01L21/027 , G03F1/36
摘要: A method for forming a photomask is provided. The method includes: receiving an initial layout including a plurality of first patterns and a plurality of second patterns; decomposing the initial layout into a first layout including the plurality of first patterns and a second layout including the plurality of second patterns; inserting a plurality of third patterns into the first layout, wherein each of the plurality of third patterns is adjacent to at least one of the plurality of first patterns; comparing the first layout and the second layout; identifying a fourth pattern as an overlapping portion of the plurality of third patterns overlapping one of the plurality of second patterns; increasing a width of the fourth pattern; and outputting the first layout including the first patterns, the third patterns and the fourth patterns into a first photomask.
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公开(公告)号:US20150087208A1
公开(公告)日:2015-03-26
申请号:US14037916
申请日:2013-09-26
发明人: CHI-MING TSAI , HAN-HSIN KUO , FU-MING HUANG , LIANG-GUANG CHEN
IPC分类号: H01L21/02 , H01L21/321
CPC分类号: H01L21/67046
摘要: In a semiconductor wafer manufacturing apparatus, a rotation module is provided to hold the semiconductor wafer at a plane. The semiconductor wafer is revolved by the rotation module around a first axis. The first axis is substantially perpendicular to the plane. A cleaning module is configured to revolve around a second axis when the cleaning module contacts the surface of the semiconductor wafer. A mechanism is further provided to enable the rotation module and/or the cleaning module to move along a direction substantially perpendicular to the first axis. Consequently, the relative velocities at the contact points between the semiconductor wafer and the cleaning module are changed. Moreover, no relative velocity at any contact point between the semiconductor wafer and the cleaning module is zero or close to zero.
摘要翻译: 在半导体晶片制造装置中,设置旋转模块以将半导体晶片保持在平面。 半导体晶片围绕第一轴线由旋转模块旋转。 第一轴基本垂直于该平面。 清洁模块构造成当清洁模块接触半导体晶片的表面时围绕第二轴旋转。 还提供一种机构,以使得旋转模块和/或清洁模块能够沿着基本上垂直于第一轴线的方向移动。 因此,改变半导体晶片和清洁模块之间的接触点处的相对速度。 此外,在半导体晶片和清洁模块之间的任何接触点处的相对速度都不为零或接近零。
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公开(公告)号:US20240312939A1
公开(公告)日:2024-09-19
申请号:US18674950
申请日:2024-05-27
发明人: MING-HO TSAI , JYUN-HONG CHEN , CHUN-CHEN LIU , YU-NU HSU , PENG-REN CHEN , WEN-HAO CHENG , CHI-MING TSAI
IPC分类号: H01L23/00
CPC分类号: H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/11462 , H01L2224/11618 , H01L2224/117 , H01L2224/11849 , H01L2224/13026 , H01L2224/13147 , H01L2224/1403
摘要: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.
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