公开(公告)号：US20160300009A1

公开(公告)日：2016-10-13

申请号：US14794549

申请日：2015-07-08

Applicant: Synopsys, Inc.

Inventor： Mohamed Shaker Sarwary ,  Hans-Jorg Peter ,  Barsneya Chakrabarti ,  Fahim Rahim ,  Mohammad Homayoun Movahed-Ezazi

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/504 ,  G06F17/5045

Abstract: A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to complete. Assigning an initial state simplifies the verification of the validity of the remaining states in the sequence, thus making it more likely to reach a conclusive result and consuming less computing resources.

Abstract translation: 系统和方法使用反应初始化来促进电子逻辑设计的形式验证。 系统通过自动分配初始状态值来验证逻辑设计的一部分通过一系列状态正确地转变。 系统与校正单元进行交互以提供验证失败的有意义的反馈，使校正单元有可能纠正故障或添加允许验证完成的新约束。 分配初始状态简化了序列中剩余状态的有效性的验证，从而使其更有可能达到确定的结果并消耗较少的计算资源。

公开(公告)号：US20170024508A1

公开(公告)日：2017-01-26

申请号：US14807676

申请日：2015-07-23

Applicant: Synopsys, Inc

Inventor： Maher Mneimneh ,  Scott Cotton ,  Mohamed Shaker Sarwary ,  Fahim Rahim ,  Sudeep Mondal ,  Paras Mal Jain

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/504

Abstract: A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.

Abstract translation: 用于管理和组合验证引擎并同时应用这样的组合以用设计约束验证属性的系统和方法基于要检查的属性和可选地用户指定的预算将计算资源分配给验证引擎。 运行验证引擎，以便根据系统接收的用户指定的断言和约束验证电路的接收到的寄存器传输级（RTL）设计描述。 从这样的引擎的数据库中选择要运行的特定验证引擎，并且在顺序，并行和分布式流中指定运行顺序。

公开(公告)号：US09405872B2

公开(公告)日：2016-08-02

申请号：US14600234

申请日：2015-01-20

Applicant: Synopsys, Inc.

Inventor： Solaiman Rahim ,  Sean Safarpour ,  Shekaripuram V. Venkatesh ,  Siddharth Guha ,  Fahim Rahim

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/78 ,  G06F2217/84

Abstract: A system and methods provide for an analysis of at least a portion of an integrated circuit (IC) that comprises a plurality of modules, for the purpose of identifying signals that can be indicative of the activity of the modules. By analyzing the activity of these signal immediately before and immediately after each module going from non-idle to idle and from idle to non-idle respectively, it is possible to determine which signals provide an indication that the module should be shut down. If the module can be shut down in idle state, then these input signals may be used as control signals for this purpose. By reporting to a designer the role of such signals a simple design change for detecting the activity and controlling the module, can save on power consumption, in ways not previously detected by the designer.

Abstract translation: 为了识别可以指示模块的活动的信号，系统和方法提供对包括多个模块的集成电路（IC）的至少一部分的分析。 通过在每个模块从非空闲状态到空闲状态之前和之后立即分析这些信号的活动，分别从空闲到非空闲状态分析这些信号的活动，可以确定哪些信号提供模块应该被关闭的指示。 如果模块可以在空闲状态下关闭，那么这些输入信号可以用作这个目的的控制信号。 通过向设计人员报告这种信号的作用，用于检测活动和控制模块的简单设计更改可以以先前未被设计人员检测到的方式节省功耗。

公开(公告)号：US11907631B2

公开(公告)日：2024-02-20

申请号：US17480574

申请日：2021-09-21

Applicant: Synopsys, Inc.

Inventor： Fahim Rahim ,  Paras Mal Jain ,  Rajarshi Mukherjee ,  Deep Shah ,  Satrajit Pal ,  Dipit Ranjan Senapati ,  Abhishek Kumar

IPC: G06F30/3312 ,  G06F30/31 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/31 ,  G06F2119/12

Abstract: Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation point.

公开(公告)号：US11526641B2

公开(公告)日：2022-12-13

申请号：US17411695

申请日：2021-08-25

Applicant: Synopsys, Inc.

Inventor： Lisa McIlwain ,  Fahim Rahim ,  Guillaume Plassan ,  Dipti Ranjan Senapati

IPC: G06F30/327 ,  G06F30/3323 ,  G06F30/3312 ,  G06F30/337 ,  G06F30/396 ,  G06F30/398 ,  G06F117/04

Abstract: Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes performing a minimization of the edge function, and in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.

公开(公告)号：US10387605B2

公开(公告)日：2019-08-20

申请号：US14807676

申请日：2015-07-23

Applicant: Synopsys, Inc.

Inventor： Maher Mneimneh ,  Scott Cotton ,  Mohamed Shaker Sarwary ,  Fahim Rahim ,  Sudeep Mondal ,  Paras Mal Jain

IPC: G06F17/50

Abstract: A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.

公开(公告)号：US09721058B2

公开(公告)日：2017-08-01

申请号：US14794549

申请日：2015-07-08

Applicant: Synopsys, Inc.

Inventor： Mohamed Shaker Sarwary ,  Hans-Jorg Peter ,  Barsneya Chakrabarti ,  Fahim Rahim ,  Mohammad Homayoun Movahed-Ezazi

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/504 ,  G06F17/5045

Abstract: A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to complete. Assigning an initial state simplifies the verification of the validity of the remaining states in the sequence, thus making it more likely to reach a conclusive result and consuming less computing resources.