Invention Application
US20160300009A1 SYSTEM AND METHOD FOR REACTIVE INITIALIZATION BASED FORMAL VERIFICATION OF ELECTRONIC LOGIC DESIGN 有权
基于电子逻辑设计的基于反应初始化的形式验证的系统和方法

SYSTEM AND METHOD FOR REACTIVE INITIALIZATION BASED FORMAL VERIFICATION OF ELECTRONIC LOGIC DESIGN
Abstract:
A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to complete. Assigning an initial state simplifies the verification of the validity of the remaining states in the sequence, thus making it more likely to reach a conclusive result and consuming less computing resources.
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