公开(公告)号：US20250006542A1

公开(公告)日：2025-01-02

申请号：US18442908

申请日：2024-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtek OH ,  Kyungwook HWANG ,  Dongho KIM ,  Joonyong PARK ,  Sanghoon SONG ,  Minchul YU ,  Junsik HWANG

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/68

Abstract: A semiconductor chip wet transfer method includes: preparing a transfer substrate that includes a plurality of recesses; supplying a liquid that includes semiconductor chips onto the plurality of recesses of the transfer substrate; aligning the semiconductor chips in the plurality of recesses by sweeping, with an align bar, an upper surface of the transfer substrate supplied with the liquid; and performing cleaning by removing semiconductor chips that are not aligned in the plurality of recesses by using a first magnetic force generating device disposed facing a lower surface of the transfer substrate.

公开(公告)号：US20170077226A1

公开(公告)日：2017-03-16

申请号：US15261229

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtek OH ,  Hyeokshin KWON ,  Hwansoo SUH ,  Insu JEON

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02425 ,  H01L21/02444 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02601 ,  H01L21/02603 ,  H01L21/02631 ,  H01L21/02639 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/861

Abstract: Provided are methods of forming nanostructures, methods of manufacturing semiconductor devices using the same, and semiconductor devices including nanostructures. A method of forming a nanostructure may include forming an insulating layer and forming a nanostructure on the insulating layer. The insulating layer may have a crystal structure. The insulating layer may include an insulating two-dimensional (2D) material. The insulating 2D material may include a hexagonal boron nitride (h-BN). The insulating layer may be formed on a catalyst metal layer. The nanostructure may include at least one of silicon (Si), germanium (Ge), and SiGe. The nanostructure may include at least one nanowire.

Abstract translation: 提供形成纳米结构的方法，制造使用其的半导体器件的制造方法以及包括纳米结构的半导体器件。 形成纳米结构的方法可以包括在绝缘层上形成绝缘层并形成纳米结构。 绝缘层可以具有晶体结构。 绝缘层可以包括绝缘二维（2D）材料。 绝缘2D材料可以包括六方氮化硼（h-BN）。 绝缘层可以形成在催化剂金属层上。 纳米结构可以包括硅（Si），锗（Ge）和SiGe中的至少一种。 纳米结构可以包括至少一个纳米线。

公开(公告)号：US20240234384A1

公开(公告)日：2024-07-11

申请号：US18402416

申请日：2024-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungwook HWANG ,  Youngtek OH ,  Dongkyun KIM ,  Dongho KIM ,  Joonyong PARK ,  Sanghoon SONG ,  Minchul YU ,  Junsik HWANG

IPC: H01L25/075

CPC classification number: H01L25/0753

Abstract: A method of transferring electronic chips includes attaching, to a relay substrate, the electronic chips arranged on a base substrate, separating the electronic chips from the base substrate, wetting a target substrate using a solvent, transferring, to the target substrate, the electronic chips that are attached to the relay substrate, pressing the relay substrate in a thickness direction of the target substrate, and drying the target substrate.

公开(公告)号：US20220320135A1

公开(公告)日：2022-10-06

申请号：US17537984

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek OH ,  Hyeyoung KWON ,  Taein KIM ,  Gukhyon YON ,  Minhyun LEE

IPC: H01L27/11582

Abstract: A nonvolatile memory device includes a channel layer, a plurality of gate electrodes and a plurality of separation layers spaced apart from the channel layer and alternately arranged, a charge trap layer between the gate electrodes in the channel layer, and a charge blocking layer between the charge trap layer and the gate electrode.

公开(公告)号：US20250054813A1

公开(公告)日：2025-02-13

申请号：US18795805

申请日：2024-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  CHUNGBUK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION

Inventor： Kyungwook HWANG ,  Jaewook JEONG ,  Jonghyun JEONG ,  Minchul YU ,  Sanghoon SONG ,  Dongho KIM ,  Joonyong PARK ,  Youngtek OH ,  Junsik HWANG

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/67 ,  H01L33/00 ,  H01L33/22

Abstract: Provided are a semiconductor chip, a method of preparing a semiconductor chip, and an apparatus for manufacturing a semiconductor chip. The method includes separating a semiconductor chip from a laminate, the laminate including a substrate, a lift-off layer on the substrate, and a semiconductor layer on the lift-off layer. The method further includes removing the lift-off layer with an etchant by applying a magnetic field while contacting the laminate and the etchant, to thereby prepare a semiconductor chip.

公开(公告)号：US20240178342A1

公开(公告)日：2024-05-30

申请号：US18198089

申请日：2023-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtek OH ,  Kyungwook HWANG ,  Dongkyun KIM ,  Dongho KIM ,  Joonyong PARK ,  Sanghoon SONG ,  Minchul YU ,  Junsik HWANG

IPC: H01L33/00

CPC classification number: H01L33/005

Abstract: A chip wet-transferring device includes a chamber, a support member provided in the chamber and configured to support a transfer substrate, the transfer substrate including a plurality of grooves and on which a plurality of micro-semiconductor chips are disposed, and a magnetic field generator configured to remove a first micro-semiconductor chip from among the plurality of micro-semiconductor chips that is disposed on the transfer substrate and at least partially outside of the plurality of grooves on the transfer substrate by generating a magnetic field that moves the first micro-semiconductor chip in a direction substantially parallel with an upper surface of the transfer substrate.

公开(公告)号：US20200135878A1

公开(公告)日：2020-04-30

申请号：US16356378

申请日：2019-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek OH ,  Jinwook JUNG ,  Hyeokshin KWON ,  Wontaek SEO ,  lnsu JEON

IPC: H01L29/45 ,  H01L29/16 ,  H01L29/786

Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.

公开(公告)号：US20250022980A1

公开(公告)日：2025-01-16

申请号：US18770345

申请日：2024-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon SONG ,  Kyungwook HWANG ,  Junsik HWANG ,  Dongho KIM ,  Joonyong PARK ,  Youngtek OH ,  Minchul YU

IPC: H01L33/00

Abstract: A chemical lift-off device includes a first chamber including a first bath containing a first chemical solution and configured to receive a semiconductor light-emitting device on a substrate, such that the semiconductor light-emitting device is partially separated from the substrate by being submerged in the first chemical solution, a cleaning bath containing deionized water and configured to receive the semiconductor light-emitting device that is partially separated from the substrate, and a second chamber including a separator including a chemical solution sprayer configured to spray a second chemical solution toward the semiconductor light-emitting device that is partially separated from the substrate, such that the semiconductor light-emitting device is completely separated from the substrate by being sprayed with the second chemical solution and a recovery assembly provided at a lower portion of the separator and configured to recover the semiconductor light-emitting device that is completely separated from the substrate.

公开(公告)号：US20240234219A1

公开(公告)日：2024-07-11

申请号：US18409369

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtek OH ,  Joonyong PARK ,  Kyungwook HWANG ,  Dongkyun KIM ,  Dongho KIM ,  Sanghoon SONG ,  Minchul YU ,  Junsik HWANG

IPC: H01L21/66 ,  H01L21/683 ,  H01L25/16

CPC classification number: H01L22/22 ,  H01L21/6835 ,  H01L25/167 ,  H01L2221/68368

Abstract: A method of transferring a micro semiconductor chip and a transferring structure are provided. The method includes providing a plurality of base transferring substrates each including a plurality of grooves, aligning the plurality of base transferring substrates on a first substrate, aligning the plurality of base transferring substrates on a second substrate, providing a target transferring structure by transferring micro semiconductor chips to the base transferring substrates of the first substrate, and providing a preliminary transferring structure by transferring micro semiconductor chips to the base transferring substrates of the second substrate.

公开(公告)号：US20220238672A1

公开(公告)日：2022-07-28

申请号：US17578981

申请日：2022-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Taein KIM ,  Youngtek OH ,  Suhyeong LEE

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L27/11582

Abstract: A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×1019 cm−3 to about 10×1019 cm−3, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.